9b7dcfa333
Not all chips have the LDORDY flag, while all chips will stabilize in 10us. There is no need for two different implementations as it is safe to wait 20us on all chips. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
387 lines
13 KiB
C
387 lines
13 KiB
C
// ADC functions on STM32H7
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//
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// Copyright (C) 2020 Konstantin Vogel <konstantin.vogel@gmx.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "board/irq.h" // irq_save
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#include "board/misc.h" // timer_from_us
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#include "command.h" // shutdown
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#include "compiler.h" // ARRAY_SIZE
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#include "generic/armcm_timer.h" // udelay
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#include "gpio.h" // gpio_adc_setup
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#include "internal.h" // GPIO
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#include "sched.h" // sched_shutdown
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#if CONFIG_MACH_STM32H7
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#define ADCIN_BANK_SIZE (20)
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#define RCC_AHBENR_ADC (RCC->AHB1ENR)
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#define RCC_AHBENR_ADCEN (RCC_AHB1ENR_ADC12EN)
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#define ADC_CKMODE (0b11)
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#define ADC_ATICKS (0b101)
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#define ADC_RES (0b110)
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#define ADC_TS (ADC3_COMMON)
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#if CONFIG_MACH_STM32H723
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#define PCSEL PCSEL_RES0
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#endif
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// Number of samples is 2^OVERSAMPLES_EXPONENT (exponent can be 0-10)
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#define OVERSAMPLES_EXPONENT 3
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#define OVERSAMPLES (1 << OVERSAMPLES_EXPONENT)
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#elif CONFIG_MACH_STM32L4
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#define ADCIN_BANK_SIZE (19)
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#define RCC_AHBENR_ADC (RCC->AHB2ENR)
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#define RCC_AHBENR_ADCEN (RCC_AHB2ENR_ADCEN)
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#define ADC_CKMODE (0)
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#define ADC_ATICKS (0b100)
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#define ADC_RES (0b00)
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#define ADC_TS (ADC12_COMMON)
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#define OVERSAMPLES (0)
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#elif CONFIG_MACH_STM32G4
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#define ADCIN_BANK_SIZE (19)
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#define RCC_AHBENR_ADC (RCC->AHB2ENR)
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#define RCC_AHBENR_ADCEN (RCC_AHB2ENR_ADC12EN)
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#define ADC_CKMODE (0b11)
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#define ADC_ATICKS (0b100)
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#define ADC_RES (0b00)
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#define ADC_TS (ADC12_COMMON)
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#define ADC_CCR_TSEN (ADC_CCR_VSENSESEL)
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#define OVERSAMPLES (0)
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#endif
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#define ADC_TEMPERATURE_PIN 0xfe
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DECL_ENUMERATION("pin", "ADC_TEMPERATURE", ADC_TEMPERATURE_PIN);
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DECL_CONSTANT("ADC_MAX", 4095);
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// GPIOs like A0_C are not covered!
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// This always gives the pin connected to the positive channel
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static const uint8_t adc_pins[] = {
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#if CONFIG_MACH_STM32H7
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// ADC1
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0, // PA0_C ADC12_INP0
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0, // PA1_C ADC12_INP1
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GPIO('F', 11), // ADC1_INP2
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GPIO('A', 6), // ADC12_INP3
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GPIO('C', 4), // ADC12_INP4
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GPIO('B', 1), // ADC12_INP5
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GPIO('F', 12), // ADC1_INP6
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GPIO('A', 7), // ADC12_INP7
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GPIO('C', 5), // ADC12_INP8
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GPIO('B', 0), // ADC12_INP9
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GPIO('C', 0), // ADC123_INP10
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GPIO('C', 1), // ADC123_INP11
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GPIO('C', 2), // ADC123_INP12
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GPIO('C', 3), // ADC12_INP13
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GPIO('A', 2), // ADC12_INP14
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GPIO('A', 3), // ADC12_INP15
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GPIO('A', 0), // ADC1_INP16
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GPIO('A', 1), // ADC1_INP17
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GPIO('A', 4), // ADC12_INP18
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GPIO('A', 5), // ADC12_INP19
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// ADC2
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0, // PA0_C ADC12_INP0
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0, // PA1_C ADC12_INP1
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GPIO('F', 13), // ADC2_INP2
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GPIO('A', 6), // ADC12_INP3
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GPIO('C', 4), // ADC12_INP4
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GPIO('B', 1), // ADC12_INP5
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GPIO('F', 14), // ADC2_INP6
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GPIO('A', 7), // ADC12_INP7
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GPIO('C', 5), // ADC12_INP8
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GPIO('B', 0), // ADC12_INP9
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GPIO('C', 0), // ADC123_INP10
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GPIO('C', 1), // ADC123_INP11
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GPIO('C', 2), // ADC123_INP12
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GPIO('C', 3), // ADC12_INP13
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GPIO('A', 2), // ADC12_INP14
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GPIO('A', 3), // ADC12_INP15
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0, // dac_out1
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0, // dac_out2
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GPIO('A', 4), // ADC12_INP18
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GPIO('A', 5), // ADC12_INP19
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// ADC3
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0, // PC2_C ADC3_INP0
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0, // PC3_C ADC3_INP1
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GPIO('F', 9) , // ADC3_INP2
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GPIO('F', 7), // ADC3_INP3
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GPIO('F', 5), // ADC3_INP4
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GPIO('F', 3), // ADC3_INP5
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GPIO('F', 10), // ADC3_INP6
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GPIO('F', 8), // ADC3_INP7
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GPIO('F', 6), // ADC3_INP8
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GPIO('F', 4), // ADC3_INP9
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GPIO('C', 0), // ADC123_INP10
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GPIO('C', 1), // ADC123_INP11
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GPIO('C', 2), // ADC123_INP12
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GPIO('H', 2), // ADC3_INP13
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GPIO('H', 3), // ADC3_INP14
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GPIO('H', 4), // ADC3_INP15
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GPIO('H', 5), // ADC3_INP16
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#if CONFIG_MACH_STM32H723
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ADC_TEMPERATURE_PIN,
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0,
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#else
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0, // Vbat/4
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ADC_TEMPERATURE_PIN,// VSENSE
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#endif
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0, // VREFINT
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#elif CONFIG_MACH_STM32G4
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0, // [0] vssa
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GPIO('A', 0), // [1]
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GPIO('A', 1), // [2]
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GPIO('A', 2), // [3]
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GPIO('A', 3), // [4]
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GPIO('B', 14), // [5]
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GPIO('C', 0), // [6]
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GPIO('C', 1), // [7]
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GPIO('C', 2), // [8]
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GPIO('C', 3), // [9]
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GPIO('F', 0), // [10]
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GPIO('B', 12), // [11]
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GPIO('B', 1), // [12]
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0, // [13] opamp
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GPIO('B', 11), // [14]
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GPIO('B', 0), // [15]
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ADC_TEMPERATURE_PIN, // [16] vtemp
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0, // [17] vbat/3
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0, // [18] vref
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0, // [0] vssa ADC 2
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GPIO('A', 0), // [1]
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GPIO('A', 1), // [2]
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GPIO('A', 6), // [3]
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GPIO('A', 7), // [4]
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GPIO('C', 4), // [5]
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GPIO('C', 0), // [6]
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GPIO('C', 1), // [7]
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GPIO('C', 2), // [8]
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GPIO('C', 3), // [9]
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GPIO('F', 1), // [10]
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GPIO('C', 5), // [11]
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GPIO('B', 2), // [12]
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GPIO('A', 5), // [13]
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GPIO('B', 11), // [14]
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GPIO('B', 15), // [15]
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0, // [16] opamp
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GPIO('A', 4), // [17]
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0, // [18] opamp
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#else // stm32l4
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0, // vref
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GPIO('C', 0), // ADC12_IN1 .. 16
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GPIO('C', 1),
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GPIO('C', 2),
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GPIO('C', 3),
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GPIO('A', 0),
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GPIO('A', 1),
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GPIO('A', 2),
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GPIO('A', 3),
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GPIO('A', 4),
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GPIO('A', 5),
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GPIO('A', 6),
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GPIO('A', 7),
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GPIO('C', 4),
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GPIO('C', 5),
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GPIO('B', 0),
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GPIO('B', 1),
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ADC_TEMPERATURE_PIN, // temp
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0, // vbat
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#endif
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};
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// ADC timing:
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// ADC clock=30Mhz, Tconv=6.5, Tsamp=64.5, total=2.3666us*OVERSAMPLES
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struct gpio_adc
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gpio_adc_setup(uint32_t pin)
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{
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// Find pin in adc_pins table
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int chan;
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for (chan=0; ; chan++) {
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if (chan >= ARRAY_SIZE(adc_pins))
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shutdown("Not a valid ADC pin");
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if (adc_pins[chan] == pin)
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break;
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}
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// Determine which ADC block to use, enable peripheral clock
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// (SYSCLK 480Mhz) /HPRE(2) /CKMODE divider(4) /additional divider(2)
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// (ADC clock 30Mhz)
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ADC_TypeDef *adc;
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#ifdef ADC3
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if (chan >= 2 * ADCIN_BANK_SIZE){
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adc = ADC3;
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if (!is_enabled_pclock(ADC3_BASE)) {
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enable_pclock(ADC3_BASE);
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}
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MODIFY_REG(ADC3_COMMON->CCR, ADC_CCR_CKMODE_Msk,
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ADC_CKMODE << ADC_CCR_CKMODE_Pos);
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chan -= 2 * ADCIN_BANK_SIZE;
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} else
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#endif
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#ifdef ADC2
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if (chan >= ADCIN_BANK_SIZE){
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adc = ADC2;
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RCC_AHBENR_ADC |= RCC_AHBENR_ADCEN;
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MODIFY_REG(ADC12_COMMON->CCR, ADC_CCR_CKMODE_Msk,
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ADC_CKMODE << ADC_CCR_CKMODE_Pos);
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chan -= ADCIN_BANK_SIZE;
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} else
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#endif
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{
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adc = ADC1;
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RCC_AHBENR_ADC |= RCC_AHBENR_ADCEN;
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MODIFY_REG(ADC12_COMMON->CCR, ADC_CCR_CKMODE_Msk,
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ADC_CKMODE << ADC_CCR_CKMODE_Pos);
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}
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// Enable the ADC
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if (!(adc->CR & ADC_CR_ADEN)) {
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// STM32H723 ADC3 and ADC1/2 registers are slightly different
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uint8_t is_stm32h723_adc3 = 0;
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#if CONFIG_MACH_STM32H723
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if (adc == ADC3) {
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is_stm32h723_adc3 = 1;
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}
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#endif
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// Pwr
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// Exit deep power down
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MODIFY_REG(adc->CR, ADC_CR_DEEPPWD_Msk, 0);
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// Switch on voltage regulator
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adc->CR |= ADC_CR_ADVREGEN;
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// Wait for voltage regulator to stabilize
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uint32_t end = timer_read_time() + timer_from_us(20);
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while (timer_is_before(timer_read_time(), end))
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;
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// Set Boost mode for 25Mhz < ADC clock <= 50Mhz
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#ifdef ADC_CR_BOOST
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MODIFY_REG(adc->CR, ADC_CR_BOOST_Msk, 0b11 << ADC_CR_BOOST_Pos);
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#endif
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// Calibration
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// Set calibration mode to Single ended (not differential)
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MODIFY_REG(adc->CR, ADC_CR_ADCALDIF_Msk, 0);
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// Enable linearity calibration
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#ifdef ADC_CR_ADCALLIN
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MODIFY_REG(adc->CR, ADC_CR_ADCALLIN_Msk, ADC_CR_ADCALLIN);
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#endif
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// Start the calibration
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MODIFY_REG(adc->CR, ADC_CR_ADCAL_Msk, ADC_CR_ADCAL);
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while(adc->CR & ADC_CR_ADCAL)
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;
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// Enable ADC
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// "Clear the ADRDY bit in the ADC_ISR register by writing ‘1’"
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adc->ISR |= ADC_ISR_ADRDY;
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adc->ISR; // Dummy read to make sure write is flushed
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adc->CR |= ADC_CR_ADEN;
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while(!(adc->ISR & ADC_ISR_ADRDY))
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;
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// Set 64.5 ADC clock cycles sample time for every channel
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// (Reference manual pg.940)
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uint32_t aticks = ADC_ATICKS;
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// Channel 0-9
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adc->SMPR1 = (aticks | (aticks << 3) | (aticks << 6)
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| (aticks << 9) | (aticks << 12) | (aticks << 15)
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| (aticks << 18) | (aticks << 21) | (aticks << 24)
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| (aticks << 27));
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// Channel 10-19
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adc->SMPR2 = (aticks | (aticks << 3) | (aticks << 6)
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| (aticks << 9) | (aticks << 12) | (aticks << 15)
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| (aticks << 18) | (aticks << 21) | (aticks << 24)
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| (aticks << 27));
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// Disable Continuous Mode
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MODIFY_REG(adc->CFGR, ADC_CFGR_CONT_Msk, 0);
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// Set to 12 bit
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if (is_stm32h723_adc3) {
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#ifdef ADC3_CFGR_RES
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MODIFY_REG(adc->CFGR, ADC3_CFGR_RES_Msk, 0 << ADC3_CFGR_RES_Pos);
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MODIFY_REG(adc->CFGR, ADC3_CFGR_ALIGN_Msk, 0<<ADC3_CFGR_ALIGN_Pos);
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#endif
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} else {
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MODIFY_REG(adc->CFGR, ADC_CFGR_RES_Msk, ADC_RES<<ADC_CFGR_RES_Pos);
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}
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#if CONFIG_MACH_STM32H7
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// Set hardware oversampling
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MODIFY_REG(adc->CFGR2, ADC_CFGR2_ROVSE_Msk, ADC_CFGR2_ROVSE);
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if (is_stm32h723_adc3) {
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#ifdef ADC3_CFGR2_OVSR
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MODIFY_REG(adc->CFGR2, ADC3_CFGR2_OVSR_Msk,
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(OVERSAMPLES_EXPONENT - 1) << ADC3_CFGR2_OVSR_Pos);
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#endif
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} else {
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MODIFY_REG(adc->CFGR2, ADC_CFGR2_OVSR_Msk,
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(OVERSAMPLES - 1) << ADC_CFGR2_OVSR_Pos);
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}
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MODIFY_REG(adc->CFGR2, ADC_CFGR2_OVSS_Msk,
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OVERSAMPLES_EXPONENT << ADC_CFGR2_OVSS_Pos);
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#else // stm32l4
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adc->CFGR |= ADC_CFGR_JQDIS | ADC_CFGR_OVRMOD;
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#endif
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}
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if (pin == ADC_TEMPERATURE_PIN) {
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ADC_TS->CCR |= ADC_CCR_TSEN;
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} else {
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gpio_peripheral(pin, GPIO_ANALOG, 0);
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}
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// Preselect (connect) channel
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#ifdef ADC_PCSEL_PCSEL
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adc->PCSEL |= (1 << chan);
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#endif
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return (struct gpio_adc){ .adc = adc, .chan = chan };
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}
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// Try to sample a value. Returns zero if sample ready, otherwise
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// returns the number of clock ticks the caller should wait before
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// retrying this function.
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uint32_t
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gpio_adc_sample(struct gpio_adc g)
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{
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ADC_TypeDef *adc = g.adc;
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uint32_t cr = adc->CR;
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if (cr & ADC_CR_ADSTART)
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goto need_delay;
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if (adc->ISR & ADC_ISR_EOC) {
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if (adc->SQR1 == (g.chan << ADC_SQR1_SQ1_Pos))
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return 0;
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goto need_delay;
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}
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// Start sample
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adc->SQR1 = (g.chan << ADC_SQR1_SQ1_Pos);
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adc->CR = cr | ADC_CR_ADSTART;
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need_delay:
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return timer_from_us(20);
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}
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// Read a value; use only after gpio_adc_sample() returns zero
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uint16_t
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gpio_adc_read(struct gpio_adc g)
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{
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ADC_TypeDef *adc = g.adc;
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return adc->DR;
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}
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// Cancel a sample that may have been started with gpio_adc_sample()
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void
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gpio_adc_cancel_sample(struct gpio_adc g)
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{
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ADC_TypeDef *adc = g.adc;
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irqstatus_t flag = irq_save();
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if (adc->SQR1 == (g.chan << ADC_SQR1_SQ1_Pos)) {
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uint32_t cr = adc->CR;
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if (cr & ADC_CR_ADSTART)
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adc->CR = (cr & ~ADC_CR_ADSTART) | ADC_CR_ADSTP;
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if (adc->ISR & ADC_ISR_EOC)
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gpio_adc_read(g);
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}
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irq_restore(flag);
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}
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