377 lines
9.3 KiB
C
377 lines
9.3 KiB
C
// SAM4e8e GPIO port
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//
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// Copyright (C) 2018 Florian Heilmann <Florian.Heilmann@gmx.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "gpio.h"
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#include "sam4e.h"
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#include "autoconf.h" // CONFIG_CLOCK_FREQ
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#include "board/irq.h" // irq_save
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#include "command.h" // shutdown
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#include "sched.h" // sched_shutdown
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#define GPIO(PORT, NUM) (((PORT)-'A') * 32 + (NUM))
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#define GPIO2PORT(PIN) ((PIN) / 32)
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#define GPIO2BIT(PIN) (1<<((PIN) % 32))
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static Pio * const digital_regs[] = {
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PIOA, PIOB, PIOC, PIOD, PIOE
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};
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void
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gpio_set_peripheral(char bank, const uint32_t bit, char ptype, uint32_t pull_up) {
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Pio *regs = digital_regs[bank - 'A'];
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regs ->PIO_IDR = bit;
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// Enable peripheral for pin
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uint32_t sr;
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switch (ptype) {
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case 'A':
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sr = regs->PIO_ABCDSR[0];
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regs->PIO_ABCDSR[0] &= (~bit & sr);
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sr = regs->PIO_ABCDSR[1];
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regs->PIO_ABCDSR[1] &= (~bit & sr);
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break;
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case 'B':
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sr = regs->PIO_ABCDSR[0];
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regs->PIO_ABCDSR[0] = (bit | sr);
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sr = regs->PIO_ABCDSR[1];
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regs->PIO_ABCDSR[1] &= (~bit & sr);
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break;
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case 'C':
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sr = regs->PIO_ABCDSR[0];
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regs->PIO_ABCDSR[0] &= (~bit & sr);
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sr = regs->PIO_ABCDSR[1];
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regs->PIO_ABCDSR[1] = (bit | sr);
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break;
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case 'D':
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sr = regs->PIO_ABCDSR[0];
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regs->PIO_ABCDSR[0] = (bit | sr);
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sr = regs->PIO_ABCDSR[1];
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regs->PIO_ABCDSR[1] = (bit | sr);
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break;
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}
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// Disable pin in IO controller
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regs->PIO_PDR = bit;
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// Set pullup
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if (pull_up) {
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regs->PIO_PUER = bit;
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} else {
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regs->PIO_PUDR = bit;
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}
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}
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struct gpio_out
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gpio_out_setup(uint8_t pin, uint8_t val)
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{
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if (GPIO2PORT(pin) >= ARRAY_SIZE(digital_regs))
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goto fail;
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uint32_t port = GPIO2PORT(pin);
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Pio *regs = digital_regs[port];
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uint32_t bank_id = ID_PIOA + port;
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if ((PMC->PMC_PCSR0 & (1u << bank_id)) == 0) {
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PMC->PMC_PCER0 = 1 << bank_id;
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}
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struct gpio_out g = { .regs=regs, .bit=GPIO2BIT(pin) };
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gpio_out_reset(g, val);
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return g;
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fail:
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shutdown("Not an output pin");
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}
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void
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gpio_out_reset(struct gpio_out g, uint8_t val)
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{
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Pio *regs = g.regs;
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irqstatus_t flag = irq_save();
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if (val)
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regs->PIO_SODR = g.bit;
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else
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regs->PIO_CODR = g.bit;
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regs->PIO_OER = g.bit;
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regs->PIO_OWER = g.bit;
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regs->PIO_PER = g.bit;
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regs->PIO_PUDR = g.bit;
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irq_restore(flag);
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}
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void
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gpio_out_toggle_noirq(struct gpio_out g)
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{
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Pio *regs = g.regs;
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regs->PIO_ODSR ^= g.bit;
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}
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void
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gpio_out_toggle(struct gpio_out g)
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{
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irqstatus_t flag = irq_save();
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gpio_out_toggle_noirq(g);
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irq_restore(flag);
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}
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void
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gpio_out_write(struct gpio_out g, uint8_t val)
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{
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Pio *regs = g.regs;
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if (val)
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regs->PIO_SODR = g.bit;
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else
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regs->PIO_CODR = g.bit;
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}
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struct gpio_in
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gpio_in_setup(uint8_t pin, int8_t pull_up)
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{
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if (GPIO2PORT(pin) >= ARRAY_SIZE(digital_regs))
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goto fail;
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uint32_t port = GPIO2PORT(pin);
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Pio *regs = digital_regs[port];
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uint32_t bank_id = ID_PIOA + port;
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if ((PMC->PMC_PCSR0 & (1u << bank_id)) == 0) {
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PMC->PMC_PCER0 = 1 << bank_id;
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}
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struct gpio_in g = { .regs=regs, .bit=GPIO2BIT(pin) };
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gpio_in_reset(g, pull_up);
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return g;
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fail:
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shutdown("Not an input pin");
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}
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void
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gpio_in_reset(struct gpio_in g, int8_t pull_up)
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{
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Pio *regs = g.regs;
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irqstatus_t flag = irq_save();
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regs->PIO_IDR = g.bit;
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if (pull_up)
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regs->PIO_PUER = g.bit;
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else
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regs->PIO_PUDR = g.bit;
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regs->PIO_ODR = g.bit;
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regs->PIO_PER = g.bit;
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irq_restore(flag);
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}
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uint8_t
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gpio_in_read(struct gpio_in g)
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{
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Pio *regs = g.regs;
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return !!(regs->PIO_PDSR & g.bit);
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}
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/****************************************************************
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* Analog Front-End Converter (AFEC) pins (see datasheet sec. 43.5)
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****************************************************************/
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static const uint8_t afec0_pins[] = {
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//remove first channel, since it offsets the channel number: GPIO('A', 8),
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GPIO('A', 17), GPIO('A', 18), GPIO('A', 19),
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GPIO('A', 20), GPIO('B', 0), GPIO('B', 1), GPIO('C', 13),
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GPIO('C', 15), GPIO('C', 12), GPIO('C', 29), GPIO('C', 30),
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GPIO('C', 31), GPIO('C', 26), GPIO('C', 27), GPIO('C',0)
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};
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static const uint8_t afec1_pins[] = {
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GPIO('B', 2), GPIO('B', 3), GPIO('A', 21), GPIO('A', 22),
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GPIO('C', 1), GPIO('C', 2), GPIO('C', 3), GPIO('C', 4),
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/* Artificially pad this array so we can safely iterate over it */
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GPIO('B', 2), GPIO('B', 2), GPIO('B', 2), GPIO('B', 2),
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GPIO('B', 2), GPIO('B', 2), GPIO('B', 2), GPIO('B', 2)
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};
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#define ADC_FREQ_MAX 6000000UL
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DECL_CONSTANT(ADC_MAX, 4095);
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inline struct gpio_adc
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gpio_pin_to_afec(uint8_t pin)
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{
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int chan;
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Afec* afec_device;
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for (chan=0; ; chan++) {
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if (chan >= ARRAY_SIZE(afec0_pins))
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shutdown("Not a valid ADC pin");
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if (afec0_pins[chan] == pin) {
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afec_device = AFEC0;
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break;
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}
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if (afec1_pins[chan] == pin) {
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afec_device = AFEC1;
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break;
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}
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}
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return (struct gpio_adc){.pin=pin, .chan=chan, .afec=afec_device};
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}
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int
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init_afec(Afec* afec) {
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// Enable PMC
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if (afec == AFEC0)
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PMC->PMC_PCER0 = 1 << ID_AFEC0;
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else
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PMC->PMC_PCER0 = 1 << ID_AFEC1;
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// If busy, return busy
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if ((afec->AFE_ISR & AFE_ISR_DRDY) == AFE_ISR_DRDY) {
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return -1;
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}
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// Reset
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afec->AFE_CR = AFE_CR_SWRST;
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// Configure afec
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afec->AFE_MR = AFE_MR_ANACH_ALLOWED | \
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AFE_MR_PRESCAL (SystemCoreClock / (2 * ADC_FREQ_MAX) -1) | \
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AFE_MR_SETTLING_AST3 | \
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AFE_MR_TRACKTIM(2) | \
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AFE_MR_TRANSFER(1) | \
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AFE_MR_STARTUP_SUT64;
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afec->AFE_EMR = AFE_EMR_TAG | \
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AFE_EMR_RES_NO_AVERAGE | \
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AFE_EMR_STM;
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afec->AFE_ACR = AFE_ACR_IBCTL(1);
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// Disable interrupts
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afec->AFE_IDR = 0xDF00803F;
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// Disable SW triggering
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uint32_t mr = afec->AFE_MR;
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mr &= ~(AFE_MR_TRGSEL_Msk | AFE_MR_TRGEN | AFE_MR_FREERUN_ON);
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mr |= AFE_MR_TRGEN_DIS;
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afec->AFE_MR = mr;
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return 0;
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}
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void
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gpio_afec_init(void) {
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while(init_afec(AFEC0) != 0) {
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(void)(AFEC0->AFE_LCDR & AFE_LCDR_LDATA_Msk);
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}
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while(init_afec(AFEC1) != 0) {
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(void)(AFEC1->AFE_LCDR & AFE_LCDR_LDATA_Msk);
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}
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}
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DECL_INIT(gpio_afec_init);
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struct gpio_adc
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gpio_adc_setup(uint8_t pin)
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{
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struct gpio_adc adc_pin = gpio_pin_to_afec(pin);
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Afec *afec = adc_pin.afec;
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//config channel
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uint32_t reg = afec->AFE_DIFFR;
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reg &= ~(1u << adc_pin.chan);
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afec->AFE_DIFFR = reg;
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reg = afec->AFE_CGR;
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reg &= ~(0x03u << (2 * adc_pin.chan));
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reg |= 1 << (2 * adc_pin.chan);
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afec->AFE_CGR = reg;
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// Configure channel
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// afec_ch_get_config_defaults(&ch_cfg);
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// afec_ch_set_config(adc_pin.afec, adc_pin.chan, &ch_cfg);
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// Remove default internal offset from channel
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// See Atmel Appnote AT03078 Section 1.5
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afec->AFE_CSELR = adc_pin.chan;
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afec->AFE_COCR = (0x800 & AFE_COCR_AOFF_Msk);
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// Enable and calibrate Channel
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afec->AFE_CHER = 1 << adc_pin.chan;
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reg = afec->AFE_CHSR;
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afec->AFE_CDOR = reg;
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afec->AFE_CR = AFE_CR_AUTOCAL;
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return adc_pin;
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}
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enum { AFE_DUMMY=0xff };
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uint8_t active_channel_afec0 = AFE_DUMMY;
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uint8_t active_channel_afec1 = AFE_DUMMY;
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inline uint8_t
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get_active_afec_channel(Afec* afec) {
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if (afec == AFEC0) {
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return active_channel_afec0;
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}
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return active_channel_afec1;
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}
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inline void
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set_active_afec_channel(Afec* afec, uint8_t chan) {
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if (afec == AFEC0) {
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active_channel_afec0 = chan;
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} else {
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active_channel_afec1 = chan;
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}
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}
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// Try to sample a value. Returns zero if sample ready, otherwise
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// returns the number of clock ticks the caller should wait before
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// retrying this function.
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uint32_t
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gpio_adc_sample(struct gpio_adc g)
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{
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Afec* afec = g.afec;
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if (get_active_afec_channel(afec) == g.chan) {
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if ((afec->AFE_ISR & AFE_ISR_DRDY) && (afec->AFE_ISR & (1 << g.chan))) {
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// Sample now ready
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return 0;
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} else {
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// Busy
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goto need_delay;
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}
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} else if (get_active_afec_channel(g.afec) != AFE_DUMMY) {
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goto need_delay;
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}
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afec->AFE_CHDR = 0x803F; // Disable all channels
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afec->AFE_CHER = 1 << g.chan;
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set_active_afec_channel(afec, g.chan);
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for (uint32_t chan = 0; chan < 16; ++chan)
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{
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if ((afec->AFE_ISR & (1 << chan)) != 0)
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{
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afec->AFE_CSELR = chan;
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(void)(afec->AFE_CDR);
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}
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}
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afec->AFE_CR = AFE_CR_START;
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need_delay:
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return ADC_FREQ_MAX * 10000ULL / CONFIG_CLOCK_FREQ; // about 400 mcu clock cycles or 40 afec cycles
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}
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// Read a value; use only after gpio_adc_sample() returns zero
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uint16_t
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gpio_adc_read(struct gpio_adc g)
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{
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Afec *afec = g.afec;
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set_active_afec_channel(g.afec, AFE_DUMMY);
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afec->AFE_CSELR = g.chan;
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return afec->AFE_CDR;
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}
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// Cancel a sample that may have been started with gpio_adc_sample()
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void
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gpio_adc_cancel_sample(struct gpio_adc g)
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{
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if (get_active_afec_channel(g.afec) == g.chan) {
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set_active_afec_channel(g.afec, AFE_DUMMY);
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}
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}
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