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Makefile: Reduce use of $^ in build rules

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It's rare to use all of a target's prerequisites in a recipe - replace
most cases with $< (the target's first prerequisite).

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
2019-03-02 12:01:44 -05:00
parent 9430fea2c5
commit 399d539969
5 changed files with 9 additions and 9 deletions
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4
src/stm32f1/Makefile
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@@ -47,5 +47,5 @@ $(OUT)klipper.bin: $(OUT)klipper.elf
$(Q)$(OBJCOPY) -O binary $< $@
flash: $(OUT)klipper.bin
@echo " Flashing $^ to $(FLASH_DEVICE) via stm32flash"
$(Q)stm32flash -w $(OUT)klipper.bin -v -g 0 $(FLASH_DEVICE)
@echo " Flashing $< to $(FLASH_DEVICE) via stm32flash"
$(Q)stm32flash -w $< -v -g 0 $(FLASH_DEVICE)