stm32: Add comments on PLL frequency requirements to clock setup code

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
2025-05-31 17:00:18 -04:00
parent c0ca4c5cc7
commit 105ce35e1b
9 changed files with 22 additions and 0 deletions
--- a/src/stm32/stm32h7.c
+++ b/src/stm32/stm32h7.c
@@ -82,6 +82,9 @@ gpio_clock_enable(GPIO_TypeDef *regs)
    RCC->AHB4ENR;
 }

+// PLL1 (h723) input: 2 to 16Mhz, vco: 192 to 836Mhz, output: 1.5 to 550Mhz
+// PLL1 (h743v) input: 2 to 16Mhz, vco: 192 to 960Mhz, output: 1.5 to 480Mhz
+
 #if !CONFIG_STM32_CLOCK_REF_INTERNAL
 DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
 #endif