Innotex/Klipper
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

lib: Add Atmel SAM C21 headers

Browse Source 
Signed-off-by: Luke Vuksta <wulfstawulfsta@gmail.com>
This commit is contained in:
Wulfsta
2023-01-15 18:44:25 -05:00
committed by KevinOConnor
parent 6414e1772d
commit 06e5c577bd
107 changed files with 49462 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

82
lib/samc21/samc21/include/instance/ac.h Normal file
View File

@@ -0,0 +1,82 @@
/**
* \file
*
* \brief Instance description for AC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_AC_INSTANCE_
#define _SAMC21_AC_INSTANCE_
/* ========== Register definition for AC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_AC_CTRLA (0x42005000) /**< \brief (AC) Control A */
#define REG_AC_CTRLB (0x42005001) /**< \brief (AC) Control B */
#define REG_AC_EVCTRL (0x42005002) /**< \brief (AC) Event Control */
#define REG_AC_INTENCLR (0x42005004) /**< \brief (AC) Interrupt Enable Clear */
#define REG_AC_INTENSET (0x42005005) /**< \brief (AC) Interrupt Enable Set */
#define REG_AC_INTFLAG (0x42005006) /**< \brief (AC) Interrupt Flag Status and Clear */
#define REG_AC_STATUSA (0x42005007) /**< \brief (AC) Status A */
#define REG_AC_STATUSB (0x42005008) /**< \brief (AC) Status B */
#define REG_AC_DBGCTRL (0x42005009) /**< \brief (AC) Debug Control */
#define REG_AC_WINCTRL (0x4200500A) /**< \brief (AC) Window Control */
#define REG_AC_SCALER0 (0x4200500C) /**< \brief (AC) Scaler 0 */
#define REG_AC_SCALER1 (0x4200500D) /**< \brief (AC) Scaler 1 */
#define REG_AC_SCALER2 (0x4200500E) /**< \brief (AC) Scaler 2 */
#define REG_AC_SCALER3 (0x4200500F) /**< \brief (AC) Scaler 3 */
#define REG_AC_COMPCTRL0 (0x42005010) /**< \brief (AC) Comparator Control 0 */
#define REG_AC_COMPCTRL1 (0x42005014) /**< \brief (AC) Comparator Control 1 */
#define REG_AC_COMPCTRL2 (0x42005018) /**< \brief (AC) Comparator Control 2 */
#define REG_AC_COMPCTRL3 (0x4200501C) /**< \brief (AC) Comparator Control 3 */
#define REG_AC_SYNCBUSY (0x42005020) /**< \brief (AC) Synchronization Busy */
#else
#define REG_AC_CTRLA (*(RwReg8 *)0x42005000UL) /**< \brief (AC) Control A */
#define REG_AC_CTRLB (*(WoReg8 *)0x42005001UL) /**< \brief (AC) Control B */
#define REG_AC_EVCTRL (*(RwReg16*)0x42005002UL) /**< \brief (AC) Event Control */
#define REG_AC_INTENCLR (*(RwReg8 *)0x42005004UL) /**< \brief (AC) Interrupt Enable Clear */
#define REG_AC_INTENSET (*(RwReg8 *)0x42005005UL) /**< \brief (AC) Interrupt Enable Set */
#define REG_AC_INTFLAG (*(RwReg8 *)0x42005006UL) /**< \brief (AC) Interrupt Flag Status and Clear */
#define REG_AC_STATUSA (*(RoReg8 *)0x42005007UL) /**< \brief (AC) Status A */
#define REG_AC_STATUSB (*(RoReg8 *)0x42005008UL) /**< \brief (AC) Status B */
#define REG_AC_DBGCTRL (*(RwReg8 *)0x42005009UL) /**< \brief (AC) Debug Control */
#define REG_AC_WINCTRL (*(RwReg8 *)0x4200500AUL) /**< \brief (AC) Window Control */
#define REG_AC_SCALER0 (*(RwReg8 *)0x4200500CUL) /**< \brief (AC) Scaler 0 */
#define REG_AC_SCALER1 (*(RwReg8 *)0x4200500DUL) /**< \brief (AC) Scaler 1 */
#define REG_AC_SCALER2 (*(RwReg8 *)0x4200500EUL) /**< \brief (AC) Scaler 2 */
#define REG_AC_SCALER3 (*(RwReg8 *)0x4200500FUL) /**< \brief (AC) Scaler 3 */
#define REG_AC_COMPCTRL0 (*(RwReg *)0x42005010UL) /**< \brief (AC) Comparator Control 0 */
#define REG_AC_COMPCTRL1 (*(RwReg *)0x42005014UL) /**< \brief (AC) Comparator Control 1 */
#define REG_AC_COMPCTRL2 (*(RwReg *)0x42005018UL) /**< \brief (AC) Comparator Control 2 */
#define REG_AC_COMPCTRL3 (*(RwReg *)0x4200501CUL) /**< \brief (AC) Comparator Control 3 */
#define REG_AC_SYNCBUSY (*(RoReg *)0x42005020UL) /**< \brief (AC) Synchronization Busy */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for AC peripheral ========== */
#define AC_COMPCTRL_MUXNEG_OPAMP 7 // OPAMP selection for MUXNEG
#define AC_GCLK_ID 40 // Index of Generic Clock
#define AC_NUM_CMP 4 // Number of comparators
#define AC_SPEED_LEVELS 2 // Number of speed values
#endif /* _SAMC21_AC_INSTANCE_ */

89
lib/samc21/samc21/include/instance/adc0.h Normal file
View File

@@ -0,0 +1,89 @@
/**
* \file
*
* \brief Instance description for ADC0
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_ADC0_INSTANCE_
#define _SAMC21_ADC0_INSTANCE_
/* ========== Register definition for ADC0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_ADC0_CTRLA (0x42004400) /**< \brief (ADC0) Control A */
#define REG_ADC0_CTRLB (0x42004401) /**< \brief (ADC0) Control B */
#define REG_ADC0_REFCTRL (0x42004402) /**< \brief (ADC0) Reference Control */
#define REG_ADC0_EVCTRL (0x42004403) /**< \brief (ADC0) Event Control */
#define REG_ADC0_INTENCLR (0x42004404) /**< \brief (ADC0) Interrupt Enable Clear */
#define REG_ADC0_INTENSET (0x42004405) /**< \brief (ADC0) Interrupt Enable Set */
#define REG_ADC0_INTFLAG (0x42004406) /**< \brief (ADC0) Interrupt Flag Status and Clear */
#define REG_ADC0_SEQSTATUS (0x42004407) /**< \brief (ADC0) Sequence Status */
#define REG_ADC0_INPUTCTRL (0x42004408) /**< \brief (ADC0) Input Control */
#define REG_ADC0_CTRLC (0x4200440A) /**< \brief (ADC0) Control C */
#define REG_ADC0_AVGCTRL (0x4200440C) /**< \brief (ADC0) Average Control */
#define REG_ADC0_SAMPCTRL (0x4200440D) /**< \brief (ADC0) Sample Time Control */
#define REG_ADC0_WINLT (0x4200440E) /**< \brief (ADC0) Window Monitor Lower Threshold */
#define REG_ADC0_WINUT (0x42004410) /**< \brief (ADC0) Window Monitor Upper Threshold */
#define REG_ADC0_GAINCORR (0x42004412) /**< \brief (ADC0) Gain Correction */
#define REG_ADC0_OFFSETCORR (0x42004414) /**< \brief (ADC0) Offset Correction */
#define REG_ADC0_SWTRIG (0x42004418) /**< \brief (ADC0) Software Trigger */
#define REG_ADC0_DBGCTRL (0x4200441C) /**< \brief (ADC0) Debug Control */
#define REG_ADC0_SYNCBUSY (0x42004420) /**< \brief (ADC0) Synchronization Busy */
#define REG_ADC0_RESULT (0x42004424) /**< \brief (ADC0) Result */
#define REG_ADC0_SEQCTRL (0x42004428) /**< \brief (ADC0) Sequence Control */
#define REG_ADC0_CALIB (0x4200442C) /**< \brief (ADC0) Calibration */
#else
#define REG_ADC0_CTRLA (*(RwReg8 *)0x42004400UL) /**< \brief (ADC0) Control A */
#define REG_ADC0_CTRLB (*(RwReg8 *)0x42004401UL) /**< \brief (ADC0) Control B */
#define REG_ADC0_REFCTRL (*(RwReg8 *)0x42004402UL) /**< \brief (ADC0) Reference Control */
#define REG_ADC0_EVCTRL (*(RwReg8 *)0x42004403UL) /**< \brief (ADC0) Event Control */
#define REG_ADC0_INTENCLR (*(RwReg8 *)0x42004404UL) /**< \brief (ADC0) Interrupt Enable Clear */
#define REG_ADC0_INTENSET (*(RwReg8 *)0x42004405UL) /**< \brief (ADC0) Interrupt Enable Set */
#define REG_ADC0_INTFLAG (*(RwReg8 *)0x42004406UL) /**< \brief (ADC0) Interrupt Flag Status and Clear */
#define REG_ADC0_SEQSTATUS (*(RoReg8 *)0x42004407UL) /**< \brief (ADC0) Sequence Status */
#define REG_ADC0_INPUTCTRL (*(RwReg16*)0x42004408UL) /**< \brief (ADC0) Input Control */
#define REG_ADC0_CTRLC (*(RwReg16*)0x4200440AUL) /**< \brief (ADC0) Control C */
#define REG_ADC0_AVGCTRL (*(RwReg8 *)0x4200440CUL) /**< \brief (ADC0) Average Control */
#define REG_ADC0_SAMPCTRL (*(RwReg8 *)0x4200440DUL) /**< \brief (ADC0) Sample Time Control */
#define REG_ADC0_WINLT (*(RwReg16*)0x4200440EUL) /**< \brief (ADC0) Window Monitor Lower Threshold */
#define REG_ADC0_WINUT (*(RwReg16*)0x42004410UL) /**< \brief (ADC0) Window Monitor Upper Threshold */
#define REG_ADC0_GAINCORR (*(RwReg16*)0x42004412UL) /**< \brief (ADC0) Gain Correction */
#define REG_ADC0_OFFSETCORR (*(RwReg16*)0x42004414UL) /**< \brief (ADC0) Offset Correction */
#define REG_ADC0_SWTRIG (*(RwReg8 *)0x42004418UL) /**< \brief (ADC0) Software Trigger */
#define REG_ADC0_DBGCTRL (*(RwReg8 *)0x4200441CUL) /**< \brief (ADC0) Debug Control */
#define REG_ADC0_SYNCBUSY (*(RoReg16*)0x42004420UL) /**< \brief (ADC0) Synchronization Busy */
#define REG_ADC0_RESULT (*(RoReg16*)0x42004424UL) /**< \brief (ADC0) Result */
#define REG_ADC0_SEQCTRL (*(RwReg *)0x42004428UL) /**< \brief (ADC0) Sequence Control */
#define REG_ADC0_CALIB (*(RwReg16*)0x4200442CUL) /**< \brief (ADC0) Calibration */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for ADC0 peripheral ========== */
#define ADC0_DMAC_ID_RESRDY 42 // index of DMA RESRDY trigger
#define ADC0_EXTCHANNEL_MSB 11 // Number of external channels
#define ADC0_GCLK_ID 33 // index of Generic Clock
#define ADC0_INT_CH30 0 // Select OPAMP or CTAT on Channel 30
#define ADC0_MASTER_SLAVE_MODE 1 // ADC Master/Slave Mode
#endif /* _SAMC21_ADC0_INSTANCE_ */

89
lib/samc21/samc21/include/instance/adc1.h Normal file
View File

@@ -0,0 +1,89 @@
/**
* \file
*
* \brief Instance description for ADC1
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_ADC1_INSTANCE_
#define _SAMC21_ADC1_INSTANCE_
/* ========== Register definition for ADC1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_ADC1_CTRLA (0x42004800) /**< \brief (ADC1) Control A */
#define REG_ADC1_CTRLB (0x42004801) /**< \brief (ADC1) Control B */
#define REG_ADC1_REFCTRL (0x42004802) /**< \brief (ADC1) Reference Control */
#define REG_ADC1_EVCTRL (0x42004803) /**< \brief (ADC1) Event Control */
#define REG_ADC1_INTENCLR (0x42004804) /**< \brief (ADC1) Interrupt Enable Clear */
#define REG_ADC1_INTENSET (0x42004805) /**< \brief (ADC1) Interrupt Enable Set */
#define REG_ADC1_INTFLAG (0x42004806) /**< \brief (ADC1) Interrupt Flag Status and Clear */
#define REG_ADC1_SEQSTATUS (0x42004807) /**< \brief (ADC1) Sequence Status */
#define REG_ADC1_INPUTCTRL (0x42004808) /**< \brief (ADC1) Input Control */
#define REG_ADC1_CTRLC (0x4200480A) /**< \brief (ADC1) Control C */
#define REG_ADC1_AVGCTRL (0x4200480C) /**< \brief (ADC1) Average Control */
#define REG_ADC1_SAMPCTRL (0x4200480D) /**< \brief (ADC1) Sample Time Control */
#define REG_ADC1_WINLT (0x4200480E) /**< \brief (ADC1) Window Monitor Lower Threshold */
#define REG_ADC1_WINUT (0x42004810) /**< \brief (ADC1) Window Monitor Upper Threshold */
#define REG_ADC1_GAINCORR (0x42004812) /**< \brief (ADC1) Gain Correction */
#define REG_ADC1_OFFSETCORR (0x42004814) /**< \brief (ADC1) Offset Correction */
#define REG_ADC1_SWTRIG (0x42004818) /**< \brief (ADC1) Software Trigger */
#define REG_ADC1_DBGCTRL (0x4200481C) /**< \brief (ADC1) Debug Control */
#define REG_ADC1_SYNCBUSY (0x42004820) /**< \brief (ADC1) Synchronization Busy */
#define REG_ADC1_RESULT (0x42004824) /**< \brief (ADC1) Result */
#define REG_ADC1_SEQCTRL (0x42004828) /**< \brief (ADC1) Sequence Control */
#define REG_ADC1_CALIB (0x4200482C) /**< \brief (ADC1) Calibration */
#else
#define REG_ADC1_CTRLA (*(RwReg8 *)0x42004800UL) /**< \brief (ADC1) Control A */
#define REG_ADC1_CTRLB (*(RwReg8 *)0x42004801UL) /**< \brief (ADC1) Control B */
#define REG_ADC1_REFCTRL (*(RwReg8 *)0x42004802UL) /**< \brief (ADC1) Reference Control */
#define REG_ADC1_EVCTRL (*(RwReg8 *)0x42004803UL) /**< \brief (ADC1) Event Control */
#define REG_ADC1_INTENCLR (*(RwReg8 *)0x42004804UL) /**< \brief (ADC1) Interrupt Enable Clear */
#define REG_ADC1_INTENSET (*(RwReg8 *)0x42004805UL) /**< \brief (ADC1) Interrupt Enable Set */
#define REG_ADC1_INTFLAG (*(RwReg8 *)0x42004806UL) /**< \brief (ADC1) Interrupt Flag Status and Clear */
#define REG_ADC1_SEQSTATUS (*(RoReg8 *)0x42004807UL) /**< \brief (ADC1) Sequence Status */
#define REG_ADC1_INPUTCTRL (*(RwReg16*)0x42004808UL) /**< \brief (ADC1) Input Control */
#define REG_ADC1_CTRLC (*(RwReg16*)0x4200480AUL) /**< \brief (ADC1) Control C */
#define REG_ADC1_AVGCTRL (*(RwReg8 *)0x4200480CUL) /**< \brief (ADC1) Average Control */
#define REG_ADC1_SAMPCTRL (*(RwReg8 *)0x4200480DUL) /**< \brief (ADC1) Sample Time Control */
#define REG_ADC1_WINLT (*(RwReg16*)0x4200480EUL) /**< \brief (ADC1) Window Monitor Lower Threshold */
#define REG_ADC1_WINUT (*(RwReg16*)0x42004810UL) /**< \brief (ADC1) Window Monitor Upper Threshold */
#define REG_ADC1_GAINCORR (*(RwReg16*)0x42004812UL) /**< \brief (ADC1) Gain Correction */
#define REG_ADC1_OFFSETCORR (*(RwReg16*)0x42004814UL) /**< \brief (ADC1) Offset Correction */
#define REG_ADC1_SWTRIG (*(RwReg8 *)0x42004818UL) /**< \brief (ADC1) Software Trigger */
#define REG_ADC1_DBGCTRL (*(RwReg8 *)0x4200481CUL) /**< \brief (ADC1) Debug Control */
#define REG_ADC1_SYNCBUSY (*(RoReg16*)0x42004820UL) /**< \brief (ADC1) Synchronization Busy */
#define REG_ADC1_RESULT (*(RoReg16*)0x42004824UL) /**< \brief (ADC1) Result */
#define REG_ADC1_SEQCTRL (*(RwReg *)0x42004828UL) /**< \brief (ADC1) Sequence Control */
#define REG_ADC1_CALIB (*(RwReg16*)0x4200482CUL) /**< \brief (ADC1) Calibration */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for ADC1 peripheral ========== */
#define ADC1_DMAC_ID_RESRDY 43 // index of DMA RESRDY trigger
#define ADC1_EXTCHANNEL_MSB 11 // Number of external channels
#define ADC1_GCLK_ID 34 // index of Generic Clock
#define ADC1_INT_CH30 0 // Select OPAMP or CTAT on Channel 30
#define ADC1_MASTER_SLAVE_MODE 2 // ADC Master/Slave Mode
#endif /* _SAMC21_ADC1_INSTANCE_ */

139
lib/samc21/samc21/include/instance/can0.h Normal file
View File

@@ -0,0 +1,139 @@
/**
* \file
*
* \brief Instance description for CAN0
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_CAN0_INSTANCE_
#define _SAMC21_CAN0_INSTANCE_
/* ========== Register definition for CAN0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CAN0_CREL (0x42001C00) /**< \brief (CAN0) Core Release */
#define REG_CAN0_ENDN (0x42001C04) /**< \brief (CAN0) Endian */
#define REG_CAN0_MRCFG (0x42001C08) /**< \brief (CAN0) Message RAM Configuration */
#define REG_CAN0_DBTP (0x42001C0C) /**< \brief (CAN0) Fast Bit Timing and Prescaler */
#define REG_CAN0_TEST (0x42001C10) /**< \brief (CAN0) Test */
#define REG_CAN0_RWD (0x42001C14) /**< \brief (CAN0) RAM Watchdog */
#define REG_CAN0_CCCR (0x42001C18) /**< \brief (CAN0) CC Control */
#define REG_CAN0_NBTP (0x42001C1C) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */
#define REG_CAN0_TSCC (0x42001C20) /**< \brief (CAN0) Timestamp Counter Configuration */
#define REG_CAN0_TSCV (0x42001C24) /**< \brief (CAN0) Timestamp Counter Value */
#define REG_CAN0_TOCC (0x42001C28) /**< \brief (CAN0) Timeout Counter Configuration */
#define REG_CAN0_TOCV (0x42001C2C) /**< \brief (CAN0) Timeout Counter Value */
#define REG_CAN0_ECR (0x42001C40) /**< \brief (CAN0) Error Counter */
#define REG_CAN0_PSR (0x42001C44) /**< \brief (CAN0) Protocol Status */
#define REG_CAN0_TDCR (0x42001C48) /**< \brief (CAN0) Extended ID Filter Configuration */
#define REG_CAN0_IR (0x42001C50) /**< \brief (CAN0) Interrupt */
#define REG_CAN0_IE (0x42001C54) /**< \brief (CAN0) Interrupt Enable */
#define REG_CAN0_ILS (0x42001C58) /**< \brief (CAN0) Interrupt Line Select */
#define REG_CAN0_ILE (0x42001C5C) /**< \brief (CAN0) Interrupt Line Enable */
#define REG_CAN0_GFC (0x42001C80) /**< \brief (CAN0) Global Filter Configuration */
#define REG_CAN0_SIDFC (0x42001C84) /**< \brief (CAN0) Standard ID Filter Configuration */
#define REG_CAN0_XIDFC (0x42001C88) /**< \brief (CAN0) Extended ID Filter Configuration */
#define REG_CAN0_XIDAM (0x42001C90) /**< \brief (CAN0) Extended ID AND Mask */
#define REG_CAN0_HPMS (0x42001C94) /**< \brief (CAN0) High Priority Message Status */
#define REG_CAN0_NDAT1 (0x42001C98) /**< \brief (CAN0) New Data 1 */
#define REG_CAN0_NDAT2 (0x42001C9C) /**< \brief (CAN0) New Data 2 */
#define REG_CAN0_RXF0C (0x42001CA0) /**< \brief (CAN0) Rx FIFO 0 Configuration */
#define REG_CAN0_RXF0S (0x42001CA4) /**< \brief (CAN0) Rx FIFO 0 Status */
#define REG_CAN0_RXF0A (0x42001CA8) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */
#define REG_CAN0_RXBC (0x42001CAC) /**< \brief (CAN0) Rx Buffer Configuration */
#define REG_CAN0_RXF1C (0x42001CB0) /**< \brief (CAN0) Rx FIFO 1 Configuration */
#define REG_CAN0_RXF1S (0x42001CB4) /**< \brief (CAN0) Rx FIFO 1 Status */
#define REG_CAN0_RXF1A (0x42001CB8) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */
#define REG_CAN0_RXESC (0x42001CBC) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */
#define REG_CAN0_TXBC (0x42001CC0) /**< \brief (CAN0) Tx Buffer Configuration */
#define REG_CAN0_TXFQS (0x42001CC4) /**< \brief (CAN0) Tx FIFO / Queue Status */
#define REG_CAN0_TXESC (0x42001CC8) /**< \brief (CAN0) Tx Buffer Element Size Configuration */
#define REG_CAN0_TXBRP (0x42001CCC) /**< \brief (CAN0) Tx Buffer Request Pending */
#define REG_CAN0_TXBAR (0x42001CD0) /**< \brief (CAN0) Tx Buffer Add Request */
#define REG_CAN0_TXBCR (0x42001CD4) /**< \brief (CAN0) Tx Buffer Cancellation Request */
#define REG_CAN0_TXBTO (0x42001CD8) /**< \brief (CAN0) Tx Buffer Transmission Occurred */
#define REG_CAN0_TXBCF (0x42001CDC) /**< \brief (CAN0) Tx Buffer Cancellation Finished */
#define REG_CAN0_TXBTIE (0x42001CE0) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */
#define REG_CAN0_TXBCIE (0x42001CE4) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */
#define REG_CAN0_TXEFC (0x42001CF0) /**< \brief (CAN0) Tx Event FIFO Configuration */
#define REG_CAN0_TXEFS (0x42001CF4) /**< \brief (CAN0) Tx Event FIFO Status */
#define REG_CAN0_TXEFA (0x42001CF8) /**< \brief (CAN0) Tx Event FIFO Acknowledge */
#else
#define REG_CAN0_CREL (*(RoReg *)0x42001C00UL) /**< \brief (CAN0) Core Release */
#define REG_CAN0_ENDN (*(RoReg *)0x42001C04UL) /**< \brief (CAN0) Endian */
#define REG_CAN0_MRCFG (*(RwReg *)0x42001C08UL) /**< \brief (CAN0) Message RAM Configuration */
#define REG_CAN0_DBTP (*(RwReg *)0x42001C0CUL) /**< \brief (CAN0) Fast Bit Timing and Prescaler */
#define REG_CAN0_TEST (*(RwReg *)0x42001C10UL) /**< \brief (CAN0) Test */
#define REG_CAN0_RWD (*(RwReg *)0x42001C14UL) /**< \brief (CAN0) RAM Watchdog */
#define REG_CAN0_CCCR (*(RwReg *)0x42001C18UL) /**< \brief (CAN0) CC Control */
#define REG_CAN0_NBTP (*(RwReg *)0x42001C1CUL) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */
#define REG_CAN0_TSCC (*(RwReg *)0x42001C20UL) /**< \brief (CAN0) Timestamp Counter Configuration */
#define REG_CAN0_TSCV (*(RoReg *)0x42001C24UL) /**< \brief (CAN0) Timestamp Counter Value */
#define REG_CAN0_TOCC (*(RwReg *)0x42001C28UL) /**< \brief (CAN0) Timeout Counter Configuration */
#define REG_CAN0_TOCV (*(RwReg *)0x42001C2CUL) /**< \brief (CAN0) Timeout Counter Value */
#define REG_CAN0_ECR (*(RoReg *)0x42001C40UL) /**< \brief (CAN0) Error Counter */
#define REG_CAN0_PSR (*(RoReg *)0x42001C44UL) /**< \brief (CAN0) Protocol Status */
#define REG_CAN0_TDCR (*(RwReg *)0x42001C48UL) /**< \brief (CAN0) Extended ID Filter Configuration */
#define REG_CAN0_IR (*(RwReg *)0x42001C50UL) /**< \brief (CAN0) Interrupt */
#define REG_CAN0_IE (*(RwReg *)0x42001C54UL) /**< \brief (CAN0) Interrupt Enable */
#define REG_CAN0_ILS (*(RwReg *)0x42001C58UL) /**< \brief (CAN0) Interrupt Line Select */
#define REG_CAN0_ILE (*(RwReg *)0x42001C5CUL) /**< \brief (CAN0) Interrupt Line Enable */
#define REG_CAN0_GFC (*(RwReg *)0x42001C80UL) /**< \brief (CAN0) Global Filter Configuration */
#define REG_CAN0_SIDFC (*(RwReg *)0x42001C84UL) /**< \brief (CAN0) Standard ID Filter Configuration */
#define REG_CAN0_XIDFC (*(RwReg *)0x42001C88UL) /**< \brief (CAN0) Extended ID Filter Configuration */
#define REG_CAN0_XIDAM (*(RwReg *)0x42001C90UL) /**< \brief (CAN0) Extended ID AND Mask */
#define REG_CAN0_HPMS (*(RoReg *)0x42001C94UL) /**< \brief (CAN0) High Priority Message Status */
#define REG_CAN0_NDAT1 (*(RwReg *)0x42001C98UL) /**< \brief (CAN0) New Data 1 */
#define REG_CAN0_NDAT2 (*(RwReg *)0x42001C9CUL) /**< \brief (CAN0) New Data 2 */
#define REG_CAN0_RXF0C (*(RwReg *)0x42001CA0UL) /**< \brief (CAN0) Rx FIFO 0 Configuration */
#define REG_CAN0_RXF0S (*(RoReg *)0x42001CA4UL) /**< \brief (CAN0) Rx FIFO 0 Status */
#define REG_CAN0_RXF0A (*(RwReg *)0x42001CA8UL) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */
#define REG_CAN0_RXBC (*(RwReg *)0x42001CACUL) /**< \brief (CAN0) Rx Buffer Configuration */
#define REG_CAN0_RXF1C (*(RwReg *)0x42001CB0UL) /**< \brief (CAN0) Rx FIFO 1 Configuration */
#define REG_CAN0_RXF1S (*(RoReg *)0x42001CB4UL) /**< \brief (CAN0) Rx FIFO 1 Status */
#define REG_CAN0_RXF1A (*(RwReg *)0x42001CB8UL) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */
#define REG_CAN0_RXESC (*(RwReg *)0x42001CBCUL) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */
#define REG_CAN0_TXBC (*(RwReg *)0x42001CC0UL) /**< \brief (CAN0) Tx Buffer Configuration */
#define REG_CAN0_TXFQS (*(RoReg *)0x42001CC4UL) /**< \brief (CAN0) Tx FIFO / Queue Status */
#define REG_CAN0_TXESC (*(RwReg *)0x42001CC8UL) /**< \brief (CAN0) Tx Buffer Element Size Configuration */
#define REG_CAN0_TXBRP (*(RoReg *)0x42001CCCUL) /**< \brief (CAN0) Tx Buffer Request Pending */
#define REG_CAN0_TXBAR (*(RwReg *)0x42001CD0UL) /**< \brief (CAN0) Tx Buffer Add Request */
#define REG_CAN0_TXBCR (*(RwReg *)0x42001CD4UL) /**< \brief (CAN0) Tx Buffer Cancellation Request */
#define REG_CAN0_TXBTO (*(RoReg *)0x42001CD8UL) /**< \brief (CAN0) Tx Buffer Transmission Occurred */
#define REG_CAN0_TXBCF (*(RoReg *)0x42001CDCUL) /**< \brief (CAN0) Tx Buffer Cancellation Finished */
#define REG_CAN0_TXBTIE (*(RwReg *)0x42001CE0UL) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */
#define REG_CAN0_TXBCIE (*(RwReg *)0x42001CE4UL) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */
#define REG_CAN0_TXEFC (*(RwReg *)0x42001CF0UL) /**< \brief (CAN0) Tx Event FIFO Configuration */
#define REG_CAN0_TXEFS (*(RoReg *)0x42001CF4UL) /**< \brief (CAN0) Tx Event FIFO Status */
#define REG_CAN0_TXEFA (*(RwReg *)0x42001CF8UL) /**< \brief (CAN0) Tx Event FIFO Acknowledge */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for CAN0 peripheral ========== */
#define CAN0_CLK_AHB_ID 8 // Index of AHB clock
#define CAN0_DMAC_ID_DEBUG 14 // DMA CAN Debug Req
#define CAN0_GCLK_ID 26 // Index of Generic Clock
#define CAN0_MSG_RAM_ADDR 0x200000000
#define CAN0_QOS_RESET_VAL 2 // QOS reset value
#endif /* _SAMC21_CAN0_INSTANCE_ */

139
lib/samc21/samc21/include/instance/can1.h Normal file
View File

@@ -0,0 +1,139 @@
/**
* \file
*
* \brief Instance description for CAN1
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_CAN1_INSTANCE_
#define _SAMC21_CAN1_INSTANCE_
/* ========== Register definition for CAN1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CAN1_CREL (0x42002000) /**< \brief (CAN1) Core Release */
#define REG_CAN1_ENDN (0x42002004) /**< \brief (CAN1) Endian */
#define REG_CAN1_MRCFG (0x42002008) /**< \brief (CAN1) Message RAM Configuration */
#define REG_CAN1_DBTP (0x4200200C) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
#define REG_CAN1_TEST (0x42002010) /**< \brief (CAN1) Test */
#define REG_CAN1_RWD (0x42002014) /**< \brief (CAN1) RAM Watchdog */
#define REG_CAN1_CCCR (0x42002018) /**< \brief (CAN1) CC Control */
#define REG_CAN1_NBTP (0x4200201C) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
#define REG_CAN1_TSCC (0x42002020) /**< \brief (CAN1) Timestamp Counter Configuration */
#define REG_CAN1_TSCV (0x42002024) /**< \brief (CAN1) Timestamp Counter Value */
#define REG_CAN1_TOCC (0x42002028) /**< \brief (CAN1) Timeout Counter Configuration */
#define REG_CAN1_TOCV (0x4200202C) /**< \brief (CAN1) Timeout Counter Value */
#define REG_CAN1_ECR (0x42002040) /**< \brief (CAN1) Error Counter */
#define REG_CAN1_PSR (0x42002044) /**< \brief (CAN1) Protocol Status */
#define REG_CAN1_TDCR (0x42002048) /**< \brief (CAN1) Extended ID Filter Configuration */
#define REG_CAN1_IR (0x42002050) /**< \brief (CAN1) Interrupt */
#define REG_CAN1_IE (0x42002054) /**< \brief (CAN1) Interrupt Enable */
#define REG_CAN1_ILS (0x42002058) /**< \brief (CAN1) Interrupt Line Select */
#define REG_CAN1_ILE (0x4200205C) /**< \brief (CAN1) Interrupt Line Enable */
#define REG_CAN1_GFC (0x42002080) /**< \brief (CAN1) Global Filter Configuration */
#define REG_CAN1_SIDFC (0x42002084) /**< \brief (CAN1) Standard ID Filter Configuration */
#define REG_CAN1_XIDFC (0x42002088) /**< \brief (CAN1) Extended ID Filter Configuration */
#define REG_CAN1_XIDAM (0x42002090) /**< \brief (CAN1) Extended ID AND Mask */
#define REG_CAN1_HPMS (0x42002094) /**< \brief (CAN1) High Priority Message Status */
#define REG_CAN1_NDAT1 (0x42002098) /**< \brief (CAN1) New Data 1 */
#define REG_CAN1_NDAT2 (0x4200209C) /**< \brief (CAN1) New Data 2 */
#define REG_CAN1_RXF0C (0x420020A0) /**< \brief (CAN1) Rx FIFO 0 Configuration */
#define REG_CAN1_RXF0S (0x420020A4) /**< \brief (CAN1) Rx FIFO 0 Status */
#define REG_CAN1_RXF0A (0x420020A8) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
#define REG_CAN1_RXBC (0x420020AC) /**< \brief (CAN1) Rx Buffer Configuration */
#define REG_CAN1_RXF1C (0x420020B0) /**< \brief (CAN1) Rx FIFO 1 Configuration */
#define REG_CAN1_RXF1S (0x420020B4) /**< \brief (CAN1) Rx FIFO 1 Status */
#define REG_CAN1_RXF1A (0x420020B8) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
#define REG_CAN1_RXESC (0x420020BC) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
#define REG_CAN1_TXBC (0x420020C0) /**< \brief (CAN1) Tx Buffer Configuration */
#define REG_CAN1_TXFQS (0x420020C4) /**< \brief (CAN1) Tx FIFO / Queue Status */
#define REG_CAN1_TXESC (0x420020C8) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
#define REG_CAN1_TXBRP (0x420020CC) /**< \brief (CAN1) Tx Buffer Request Pending */
#define REG_CAN1_TXBAR (0x420020D0) /**< \brief (CAN1) Tx Buffer Add Request */
#define REG_CAN1_TXBCR (0x420020D4) /**< \brief (CAN1) Tx Buffer Cancellation Request */
#define REG_CAN1_TXBTO (0x420020D8) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
#define REG_CAN1_TXBCF (0x420020DC) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
#define REG_CAN1_TXBTIE (0x420020E0) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
#define REG_CAN1_TXBCIE (0x420020E4) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
#define REG_CAN1_TXEFC (0x420020F0) /**< \brief (CAN1) Tx Event FIFO Configuration */
#define REG_CAN1_TXEFS (0x420020F4) /**< \brief (CAN1) Tx Event FIFO Status */
#define REG_CAN1_TXEFA (0x420020F8) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
#else
#define REG_CAN1_CREL (*(RoReg *)0x42002000UL) /**< \brief (CAN1) Core Release */
#define REG_CAN1_ENDN (*(RoReg *)0x42002004UL) /**< \brief (CAN1) Endian */
#define REG_CAN1_MRCFG (*(RwReg *)0x42002008UL) /**< \brief (CAN1) Message RAM Configuration */
#define REG_CAN1_DBTP (*(RwReg *)0x4200200CUL) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
#define REG_CAN1_TEST (*(RwReg *)0x42002010UL) /**< \brief (CAN1) Test */
#define REG_CAN1_RWD (*(RwReg *)0x42002014UL) /**< \brief (CAN1) RAM Watchdog */
#define REG_CAN1_CCCR (*(RwReg *)0x42002018UL) /**< \brief (CAN1) CC Control */
#define REG_CAN1_NBTP (*(RwReg *)0x4200201CUL) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
#define REG_CAN1_TSCC (*(RwReg *)0x42002020UL) /**< \brief (CAN1) Timestamp Counter Configuration */
#define REG_CAN1_TSCV (*(RoReg *)0x42002024UL) /**< \brief (CAN1) Timestamp Counter Value */
#define REG_CAN1_TOCC (*(RwReg *)0x42002028UL) /**< \brief (CAN1) Timeout Counter Configuration */
#define REG_CAN1_TOCV (*(RwReg *)0x4200202CUL) /**< \brief (CAN1) Timeout Counter Value */
#define REG_CAN1_ECR (*(RoReg *)0x42002040UL) /**< \brief (CAN1) Error Counter */
#define REG_CAN1_PSR (*(RoReg *)0x42002044UL) /**< \brief (CAN1) Protocol Status */
#define REG_CAN1_TDCR (*(RwReg *)0x42002048UL) /**< \brief (CAN1) Extended ID Filter Configuration */
#define REG_CAN1_IR (*(RwReg *)0x42002050UL) /**< \brief (CAN1) Interrupt */
#define REG_CAN1_IE (*(RwReg *)0x42002054UL) /**< \brief (CAN1) Interrupt Enable */
#define REG_CAN1_ILS (*(RwReg *)0x42002058UL) /**< \brief (CAN1) Interrupt Line Select */
#define REG_CAN1_ILE (*(RwReg *)0x4200205CUL) /**< \brief (CAN1) Interrupt Line Enable */
#define REG_CAN1_GFC (*(RwReg *)0x42002080UL) /**< \brief (CAN1) Global Filter Configuration */
#define REG_CAN1_SIDFC (*(RwReg *)0x42002084UL) /**< \brief (CAN1) Standard ID Filter Configuration */
#define REG_CAN1_XIDFC (*(RwReg *)0x42002088UL) /**< \brief (CAN1) Extended ID Filter Configuration */
#define REG_CAN1_XIDAM (*(RwReg *)0x42002090UL) /**< \brief (CAN1) Extended ID AND Mask */
#define REG_CAN1_HPMS (*(RoReg *)0x42002094UL) /**< \brief (CAN1) High Priority Message Status */
#define REG_CAN1_NDAT1 (*(RwReg *)0x42002098UL) /**< \brief (CAN1) New Data 1 */
#define REG_CAN1_NDAT2 (*(RwReg *)0x4200209CUL) /**< \brief (CAN1) New Data 2 */
#define REG_CAN1_RXF0C (*(RwReg *)0x420020A0UL) /**< \brief (CAN1) Rx FIFO 0 Configuration */
#define REG_CAN1_RXF0S (*(RoReg *)0x420020A4UL) /**< \brief (CAN1) Rx FIFO 0 Status */
#define REG_CAN1_RXF0A (*(RwReg *)0x420020A8UL) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
#define REG_CAN1_RXBC (*(RwReg *)0x420020ACUL) /**< \brief (CAN1) Rx Buffer Configuration */
#define REG_CAN1_RXF1C (*(RwReg *)0x420020B0UL) /**< \brief (CAN1) Rx FIFO 1 Configuration */
#define REG_CAN1_RXF1S (*(RoReg *)0x420020B4UL) /**< \brief (CAN1) Rx FIFO 1 Status */
#define REG_CAN1_RXF1A (*(RwReg *)0x420020B8UL) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
#define REG_CAN1_RXESC (*(RwReg *)0x420020BCUL) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
#define REG_CAN1_TXBC (*(RwReg *)0x420020C0UL) /**< \brief (CAN1) Tx Buffer Configuration */
#define REG_CAN1_TXFQS (*(RoReg *)0x420020C4UL) /**< \brief (CAN1) Tx FIFO / Queue Status */
#define REG_CAN1_TXESC (*(RwReg *)0x420020C8UL) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
#define REG_CAN1_TXBRP (*(RoReg *)0x420020CCUL) /**< \brief (CAN1) Tx Buffer Request Pending */
#define REG_CAN1_TXBAR (*(RwReg *)0x420020D0UL) /**< \brief (CAN1) Tx Buffer Add Request */
#define REG_CAN1_TXBCR (*(RwReg *)0x420020D4UL) /**< \brief (CAN1) Tx Buffer Cancellation Request */
#define REG_CAN1_TXBTO (*(RoReg *)0x420020D8UL) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
#define REG_CAN1_TXBCF (*(RoReg *)0x420020DCUL) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
#define REG_CAN1_TXBTIE (*(RwReg *)0x420020E0UL) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
#define REG_CAN1_TXBCIE (*(RwReg *)0x420020E4UL) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
#define REG_CAN1_TXEFC (*(RwReg *)0x420020F0UL) /**< \brief (CAN1) Tx Event FIFO Configuration */
#define REG_CAN1_TXEFS (*(RoReg *)0x420020F4UL) /**< \brief (CAN1) Tx Event FIFO Status */
#define REG_CAN1_TXEFA (*(RwReg *)0x420020F8UL) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for CAN1 peripheral ========== */
#define CAN1_CLK_AHB_ID 9 // Index of AHB clock
#define CAN1_DMAC_ID_DEBUG 15 // DMA CAN Debug Req
#define CAN1_GCLK_ID 27 // Index of Generic Clock
#define CAN1_MSG_RAM_ADDR 0x200000000
#define CAN1_QOS_RESET_VAL 2 // QOS reset value
#endif /* _SAMC21_CAN1_INSTANCE_ */

58
lib/samc21/samc21/include/instance/ccl.h Normal file
View File

@@ -0,0 +1,58 @@
/**
* \file
*
* \brief Instance description for CCL
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_CCL_INSTANCE_
#define _SAMC21_CCL_INSTANCE_
/* ========== Register definition for CCL peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CCL_CTRL (0x42005C00) /**< \brief (CCL) Control */
#define REG_CCL_SEQCTRL0 (0x42005C04) /**< \brief (CCL) SEQ Control x 0 */
#define REG_CCL_SEQCTRL1 (0x42005C05) /**< \brief (CCL) SEQ Control x 1 */
#define REG_CCL_LUTCTRL0 (0x42005C08) /**< \brief (CCL) LUT Control x 0 */
#define REG_CCL_LUTCTRL1 (0x42005C0C) /**< \brief (CCL) LUT Control x 1 */
#define REG_CCL_LUTCTRL2 (0x42005C10) /**< \brief (CCL) LUT Control x 2 */
#define REG_CCL_LUTCTRL3 (0x42005C14) /**< \brief (CCL) LUT Control x 3 */
#else
#define REG_CCL_CTRL (*(RwReg8 *)0x42005C00UL) /**< \brief (CCL) Control */
#define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x42005C04UL) /**< \brief (CCL) SEQ Control x 0 */
#define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42005C05UL) /**< \brief (CCL) SEQ Control x 1 */
#define REG_CCL_LUTCTRL0 (*(RwReg *)0x42005C08UL) /**< \brief (CCL) LUT Control x 0 */
#define REG_CCL_LUTCTRL1 (*(RwReg *)0x42005C0CUL) /**< \brief (CCL) LUT Control x 1 */
#define REG_CCL_LUTCTRL2 (*(RwReg *)0x42005C10UL) /**< \brief (CCL) LUT Control x 2 */
#define REG_CCL_LUTCTRL3 (*(RwReg *)0x42005C14UL) /**< \brief (CCL) LUT Control x 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for CCL peripheral ========== */
#define CCL_GCLK_ID 38 // GCLK index for CCL
#define CCL_IO_NUM 12 // Numer of input pins
#define CCL_LUT_NUM 4 // Number of LUT in a CCL
#define CCL_SEQ_NUM 2 // Number of SEQ in a CCL
#endif /* _SAMC21_CCL_INSTANCE_ */

64
lib/samc21/samc21/include/instance/dac.h Normal file
View File

@@ -0,0 +1,64 @@
/**
* \file
*
* \brief Instance description for DAC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_DAC_INSTANCE_
#define _SAMC21_DAC_INSTANCE_
/* ========== Register definition for DAC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DAC_CTRLA (0x42005400) /**< \brief (DAC) Control A */
#define REG_DAC_CTRLB (0x42005401) /**< \brief (DAC) Control B */
#define REG_DAC_EVCTRL (0x42005402) /**< \brief (DAC) Event Control */
#define REG_DAC_INTENCLR (0x42005404) /**< \brief (DAC) Interrupt Enable Clear */
#define REG_DAC_INTENSET (0x42005405) /**< \brief (DAC) Interrupt Enable Set */
#define REG_DAC_INTFLAG (0x42005406) /**< \brief (DAC) Interrupt Flag Status and Clear */
#define REG_DAC_STATUS (0x42005407) /**< \brief (DAC) Status */
#define REG_DAC_DATA (0x42005408) /**< \brief (DAC) Data */
#define REG_DAC_DATABUF (0x4200540C) /**< \brief (DAC) Data Buffer */
#define REG_DAC_SYNCBUSY (0x42005410) /**< \brief (DAC) Synchronization Busy */
#define REG_DAC_DBGCTRL (0x42005414) /**< \brief (DAC) Debug Control */
#else
#define REG_DAC_CTRLA (*(RwReg8 *)0x42005400UL) /**< \brief (DAC) Control A */
#define REG_DAC_CTRLB (*(RwReg8 *)0x42005401UL) /**< \brief (DAC) Control B */
#define REG_DAC_EVCTRL (*(RwReg8 *)0x42005402UL) /**< \brief (DAC) Event Control */
#define REG_DAC_INTENCLR (*(RwReg8 *)0x42005404UL) /**< \brief (DAC) Interrupt Enable Clear */
#define REG_DAC_INTENSET (*(RwReg8 *)0x42005405UL) /**< \brief (DAC) Interrupt Enable Set */
#define REG_DAC_INTFLAG (*(RwReg8 *)0x42005406UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
#define REG_DAC_STATUS (*(RoReg8 *)0x42005407UL) /**< \brief (DAC) Status */
#define REG_DAC_DATA (*(WoReg16*)0x42005408UL) /**< \brief (DAC) Data */
#define REG_DAC_DATABUF (*(WoReg16*)0x4200540CUL) /**< \brief (DAC) Data Buffer */
#define REG_DAC_SYNCBUSY (*(RoReg *)0x42005410UL) /**< \brief (DAC) Synchronization Busy */
#define REG_DAC_DBGCTRL (*(RwReg8 *)0x42005414UL) /**< \brief (DAC) Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DAC peripheral ========== */
#define DAC_DMAC_ID_EMPTY 45 // Index of DMA EMPTY trigger
#define DAC_GCLK_ID 36
#endif /* _SAMC21_DAC_INSTANCE_ */

55
lib/samc21/samc21/include/instance/divas.h Normal file
View File

@@ -0,0 +1,55 @@
/**
* \file
*
* \brief Instance description for DIVAS
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_DIVAS_INSTANCE_
#define _SAMC21_DIVAS_INSTANCE_
/* ========== Register definition for DIVAS peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DIVAS_CTRLA (0x48000000) /**< \brief (DIVAS) Control */
#define REG_DIVAS_STATUS (0x48000004) /**< \brief (DIVAS) Status */
#define REG_DIVAS_DIVIDEND (0x48000008) /**< \brief (DIVAS) Dividend */
#define REG_DIVAS_DIVISOR (0x4800000C) /**< \brief (DIVAS) Divisor */
#define REG_DIVAS_RESULT (0x48000010) /**< \brief (DIVAS) Result */
#define REG_DIVAS_REM (0x48000014) /**< \brief (DIVAS) Remainder */
#define REG_DIVAS_SQRNUM (0x48000018) /**< \brief (DIVAS) Square Root Input */
#else
#define REG_DIVAS_CTRLA (*(RwReg8 *)0x48000000UL) /**< \brief (DIVAS) Control */
#define REG_DIVAS_STATUS (*(RwReg8 *)0x48000004UL) /**< \brief (DIVAS) Status */
#define REG_DIVAS_DIVIDEND (*(RwReg *)0x48000008UL) /**< \brief (DIVAS) Dividend */
#define REG_DIVAS_DIVISOR (*(RwReg *)0x4800000CUL) /**< \brief (DIVAS) Divisor */
#define REG_DIVAS_RESULT (*(RoReg *)0x48000010UL) /**< \brief (DIVAS) Result */
#define REG_DIVAS_REM (*(RoReg *)0x48000014UL) /**< \brief (DIVAS) Remainder */
#define REG_DIVAS_SQRNUM (*(RwReg *)0x48000018UL) /**< \brief (DIVAS) Square Root Input */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DIVAS peripheral ========== */
#define DIVAS_CLK_AHB_ID 12 // AHB clock index
#endif /* _SAMC21_DIVAS_INSTANCE_ */

97
lib/samc21/samc21/include/instance/dmac.h Normal file
View File

@@ -0,0 +1,97 @@
/**
* \file
*
* \brief Instance description for DMAC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_DMAC_INSTANCE_
#define _SAMC21_DMAC_INSTANCE_
/* ========== Register definition for DMAC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DMAC_CTRL (0x41006000) /**< \brief (DMAC) Control */
#define REG_DMAC_CRCCTRL (0x41006002) /**< \brief (DMAC) CRC Control */
#define REG_DMAC_CRCDATAIN (0x41006004) /**< \brief (DMAC) CRC Data Input */
#define REG_DMAC_CRCCHKSUM (0x41006008) /**< \brief (DMAC) CRC Checksum */
#define REG_DMAC_CRCSTATUS (0x4100600C) /**< \brief (DMAC) CRC Status */
#define REG_DMAC_DBGCTRL (0x4100600D) /**< \brief (DMAC) Debug Control */
#define REG_DMAC_QOSCTRL (0x4100600E) /**< \brief (DMAC) QOS Control */
#define REG_DMAC_SWTRIGCTRL (0x41006010) /**< \brief (DMAC) Software Trigger Control */
#define REG_DMAC_PRICTRL0 (0x41006014) /**< \brief (DMAC) Priority Control 0 */
#define REG_DMAC_INTPEND (0x41006020) /**< \brief (DMAC) Interrupt Pending */
#define REG_DMAC_INTSTATUS (0x41006024) /**< \brief (DMAC) Interrupt Status */
#define REG_DMAC_BUSYCH (0x41006028) /**< \brief (DMAC) Busy Channels */
#define REG_DMAC_PENDCH (0x4100602C) /**< \brief (DMAC) Pending Channels */
#define REG_DMAC_ACTIVE (0x41006030) /**< \brief (DMAC) Active Channel and Levels */
#define REG_DMAC_BASEADDR (0x41006034) /**< \brief (DMAC) Descriptor Memory Section Base Address */
#define REG_DMAC_WRBADDR (0x41006038) /**< \brief (DMAC) Write-Back Memory Section Base Address */
#define REG_DMAC_CHID (0x4100603F) /**< \brief (DMAC) Channel ID */
#define REG_DMAC_CHCTRLA (0x41006040) /**< \brief (DMAC) Channel Control A */
#define REG_DMAC_CHCTRLB (0x41006044) /**< \brief (DMAC) Channel Control B */
#define REG_DMAC_CHINTENCLR (0x4100604C) /**< \brief (DMAC) Channel Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET (0x4100604D) /**< \brief (DMAC) Channel Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG (0x4100604E) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS (0x4100604F) /**< \brief (DMAC) Channel Status */
#else
#define REG_DMAC_CTRL (*(RwReg16*)0x41006000UL) /**< \brief (DMAC) Control */
#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41006002UL) /**< \brief (DMAC) CRC Control */
#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41006004UL) /**< \brief (DMAC) CRC Data Input */
#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41006008UL) /**< \brief (DMAC) CRC Checksum */
#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100600CUL) /**< \brief (DMAC) CRC Status */
#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100600DUL) /**< \brief (DMAC) Debug Control */
#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100600EUL) /**< \brief (DMAC) QOS Control */
#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41006010UL) /**< \brief (DMAC) Software Trigger Control */
#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41006014UL) /**< \brief (DMAC) Priority Control 0 */
#define REG_DMAC_INTPEND (*(RwReg16*)0x41006020UL) /**< \brief (DMAC) Interrupt Pending */
#define REG_DMAC_INTSTATUS (*(RoReg *)0x41006024UL) /**< \brief (DMAC) Interrupt Status */
#define REG_DMAC_BUSYCH (*(RoReg *)0x41006028UL) /**< \brief (DMAC) Busy Channels */
#define REG_DMAC_PENDCH (*(RoReg *)0x4100602CUL) /**< \brief (DMAC) Pending Channels */
#define REG_DMAC_ACTIVE (*(RoReg *)0x41006030UL) /**< \brief (DMAC) Active Channel and Levels */
#define REG_DMAC_BASEADDR (*(RwReg *)0x41006034UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */
#define REG_DMAC_WRBADDR (*(RwReg *)0x41006038UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */
#define REG_DMAC_CHID (*(RwReg8 *)0x4100603FUL) /**< \brief (DMAC) Channel ID */
#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41006040UL) /**< \brief (DMAC) Channel Control A */
#define REG_DMAC_CHCTRLB (*(RwReg *)0x41006044UL) /**< \brief (DMAC) Channel Control B */
#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100604CUL) /**< \brief (DMAC) Channel Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100604DUL) /**< \brief (DMAC) Channel Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100604EUL) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100604FUL) /**< \brief (DMAC) Channel Status */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DMAC peripheral ========== */
#define DMAC_CH_BITS 4 // Number of bits to select channel
#define DMAC_CLK_AHB_ID 7 // AHB clock index
#define DMAC_EVIN_NUM 4 // Number of input events
#define DMAC_EVOUT_NUM 4 // Number of output events
#define DMAC_LVL_BITS 2 // Number of bit to select level priority
#define DMAC_LVL_NUM 4 // Enable priority level number
#define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value
#define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value
#define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value
#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source
#define DMAC_TRIG_NUM 49 // Number of peripheral triggers
#endif /* _SAMC21_DMAC_INSTANCE_ */

97
lib/samc21/samc21/include/instance/dsu.h Normal file
View File

@@ -0,0 +1,97 @@
/**
* \file
*
* \brief Instance description for DSU
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_DSU_INSTANCE_
#define _SAMC21_DSU_INSTANCE_
/* ========== Register definition for DSU peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */
#define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */
#define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */
#define REG_DSU_STATUSC (0x41002003) /**< \brief (DSU) Status C */
#define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */
#define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */
#define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */
#define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */
#define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */
#define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */
#define REG_DSU_DCFG0 (0x410020F0) /**< \brief (DSU) Device Configuration 0 */
#define REG_DSU_DCFG1 (0x410020F4) /**< \brief (DSU) Device Configuration 1 */
#define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
#define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
#define REG_DSU_END (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */
#define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) CoreSight ROM Table Memory Type */
#define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */
#define REG_DSU_PID5 (0x41003FD4) /**< \brief (DSU) Peripheral Identification 5 */
#define REG_DSU_PID6 (0x41003FD8) /**< \brief (DSU) Peripheral Identification 6 */
#define REG_DSU_PID7 (0x41003FDC) /**< \brief (DSU) Peripheral Identification 7 */
#define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */
#define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */
#define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */
#define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */
#define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */
#define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */
#define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */
#define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */
#else
#define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */
#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */
#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */
#define REG_DSU_STATUSC (*(RoReg8 *)0x41002003UL) /**< \brief (DSU) Status C */
#define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */
#define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */
#define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */
#define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */
#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */
#define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */
#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0UL) /**< \brief (DSU) Device Configuration 0 */
#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4UL) /**< \brief (DSU) Device Configuration 1 */
#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
#define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */
#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table Memory Type */
#define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */
#define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identification 5 */
#define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identification 6 */
#define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identification 7 */
#define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */
#define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */
#define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */
#define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */
#define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */
#define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */
#define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */
#define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DSU peripheral ========== */
#define DSU_CLK_AHB_ID 3
#endif /* _SAMC21_DSU_INSTANCE_ */

66
lib/samc21/samc21/include/instance/eic.h Normal file
View File

@@ -0,0 +1,66 @@
/**
* \file
*
* \brief Instance description for EIC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_EIC_INSTANCE_
#define _SAMC21_EIC_INSTANCE_
/* ========== Register definition for EIC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_EIC_CTRLA (0x40002800) /**< \brief (EIC) Control */
#define REG_EIC_NMICTRL (0x40002801) /**< \brief (EIC) NMI Control */
#define REG_EIC_NMIFLAG (0x40002802) /**< \brief (EIC) NMI Interrupt Flag */
#define REG_EIC_SYNCBUSY (0x40002804) /**< \brief (EIC) Syncbusy register */
#define REG_EIC_EVCTRL (0x40002808) /**< \brief (EIC) Event Control */
#define REG_EIC_INTENCLR (0x4000280C) /**< \brief (EIC) Interrupt Enable Clear */
#define REG_EIC_INTENSET (0x40002810) /**< \brief (EIC) Interrupt Enable Set */
#define REG_EIC_INTFLAG (0x40002814) /**< \brief (EIC) Interrupt Flag Status and Clear */
#define REG_EIC_ASYNCH (0x40002818) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */
#define REG_EIC_CONFIG0 (0x4000281C) /**< \brief (EIC) Configuration 0 */
#define REG_EIC_CONFIG1 (0x40002820) /**< \brief (EIC) Configuration 1 */
#else
#define REG_EIC_CTRLA (*(RwReg8 *)0x40002800UL) /**< \brief (EIC) Control */
#define REG_EIC_NMICTRL (*(RwReg8 *)0x40002801UL) /**< \brief (EIC) NMI Control */
#define REG_EIC_NMIFLAG (*(RwReg16*)0x40002802UL) /**< \brief (EIC) NMI Interrupt Flag */
#define REG_EIC_SYNCBUSY (*(RoReg *)0x40002804UL) /**< \brief (EIC) Syncbusy register */
#define REG_EIC_EVCTRL (*(RwReg *)0x40002808UL) /**< \brief (EIC) Event Control */
#define REG_EIC_INTENCLR (*(RwReg *)0x4000280CUL) /**< \brief (EIC) Interrupt Enable Clear */
#define REG_EIC_INTENSET (*(RwReg *)0x40002810UL) /**< \brief (EIC) Interrupt Enable Set */
#define REG_EIC_INTFLAG (*(RwReg *)0x40002814UL) /**< \brief (EIC) Interrupt Flag Status and Clear */
#define REG_EIC_ASYNCH (*(RwReg *)0x40002818UL) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */
#define REG_EIC_CONFIG0 (*(RwReg *)0x4000281CUL) /**< \brief (EIC) Configuration 0 */
#define REG_EIC_CONFIG1 (*(RwReg *)0x40002820UL) /**< \brief (EIC) Configuration 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for EIC peripheral ========== */
#define EIC_EXTINT_NUM 16
#define EIC_GCLK_ID 2
#define EIC_NUMBER_OF_CONFIG_REGS 2
#define EIC_NUMBER_OF_INTERRUPTS 16
#endif /* _SAMC21_EIC_INSTANCE_ */

325
lib/samc21/samc21/include/instance/evsys.h Normal file
View File

@@ -0,0 +1,325 @@
/**
* \file
*
* \brief Instance description for EVSYS
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_EVSYS_INSTANCE_
#define _SAMC21_EVSYS_INSTANCE_
/* ========== Register definition for EVSYS peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_EVSYS_CTRLA (0x42000000) /**< \brief (EVSYS) Control */
#define REG_EVSYS_CHSTATUS (0x4200000C) /**< \brief (EVSYS) Channel Status */
#define REG_EVSYS_INTENCLR (0x42000010) /**< \brief (EVSYS) Interrupt Enable Clear */
#define REG_EVSYS_INTENSET (0x42000014) /**< \brief (EVSYS) Interrupt Enable Set */
#define REG_EVSYS_INTFLAG (0x42000018) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
#define REG_EVSYS_SWEVT (0x4200001C) /**< \brief (EVSYS) Software Event */
#define REG_EVSYS_CHANNEL0 (0x42000020) /**< \brief (EVSYS) Channel 0 */
#define REG_EVSYS_CHANNEL1 (0x42000024) /**< \brief (EVSYS) Channel 1 */
#define REG_EVSYS_CHANNEL2 (0x42000028) /**< \brief (EVSYS) Channel 2 */
#define REG_EVSYS_CHANNEL3 (0x4200002C) /**< \brief (EVSYS) Channel 3 */
#define REG_EVSYS_CHANNEL4 (0x42000030) /**< \brief (EVSYS) Channel 4 */
#define REG_EVSYS_CHANNEL5 (0x42000034) /**< \brief (EVSYS) Channel 5 */
#define REG_EVSYS_CHANNEL6 (0x42000038) /**< \brief (EVSYS) Channel 6 */
#define REG_EVSYS_CHANNEL7 (0x4200003C) /**< \brief (EVSYS) Channel 7 */
#define REG_EVSYS_CHANNEL8 (0x42000040) /**< \brief (EVSYS) Channel 8 */
#define REG_EVSYS_CHANNEL9 (0x42000044) /**< \brief (EVSYS) Channel 9 */
#define REG_EVSYS_CHANNEL10 (0x42000048) /**< \brief (EVSYS) Channel 10 */
#define REG_EVSYS_CHANNEL11 (0x4200004C) /**< \brief (EVSYS) Channel 11 */
#define REG_EVSYS_USER0 (0x42000080) /**< \brief (EVSYS) User Multiplexer 0 */
#define REG_EVSYS_USER1 (0x42000084) /**< \brief (EVSYS) User Multiplexer 1 */
#define REG_EVSYS_USER2 (0x42000088) /**< \brief (EVSYS) User Multiplexer 2 */
#define REG_EVSYS_USER3 (0x4200008C) /**< \brief (EVSYS) User Multiplexer 3 */
#define REG_EVSYS_USER4 (0x42000090) /**< \brief (EVSYS) User Multiplexer 4 */
#define REG_EVSYS_USER5 (0x42000094) /**< \brief (EVSYS) User Multiplexer 5 */
#define REG_EVSYS_USER6 (0x42000098) /**< \brief (EVSYS) User Multiplexer 6 */
#define REG_EVSYS_USER7 (0x4200009C) /**< \brief (EVSYS) User Multiplexer 7 */
#define REG_EVSYS_USER8 (0x420000A0) /**< \brief (EVSYS) User Multiplexer 8 */
#define REG_EVSYS_USER9 (0x420000A4) /**< \brief (EVSYS) User Multiplexer 9 */
#define REG_EVSYS_USER10 (0x420000A8) /**< \brief (EVSYS) User Multiplexer 10 */
#define REG_EVSYS_USER11 (0x420000AC) /**< \brief (EVSYS) User Multiplexer 11 */
#define REG_EVSYS_USER12 (0x420000B0) /**< \brief (EVSYS) User Multiplexer 12 */
#define REG_EVSYS_USER13 (0x420000B4) /**< \brief (EVSYS) User Multiplexer 13 */
#define REG_EVSYS_USER14 (0x420000B8) /**< \brief (EVSYS) User Multiplexer 14 */
#define REG_EVSYS_USER15 (0x420000BC) /**< \brief (EVSYS) User Multiplexer 15 */
#define REG_EVSYS_USER16 (0x420000C0) /**< \brief (EVSYS) User Multiplexer 16 */
#define REG_EVSYS_USER17 (0x420000C4) /**< \brief (EVSYS) User Multiplexer 17 */
#define REG_EVSYS_USER18 (0x420000C8) /**< \brief (EVSYS) User Multiplexer 18 */
#define REG_EVSYS_USER19 (0x420000CC) /**< \brief (EVSYS) User Multiplexer 19 */
#define REG_EVSYS_USER20 (0x420000D0) /**< \brief (EVSYS) User Multiplexer 20 */
#define REG_EVSYS_USER21 (0x420000D4) /**< \brief (EVSYS) User Multiplexer 21 */
#define REG_EVSYS_USER22 (0x420000D8) /**< \brief (EVSYS) User Multiplexer 22 */
#define REG_EVSYS_USER23 (0x420000DC) /**< \brief (EVSYS) User Multiplexer 23 */
#define REG_EVSYS_USER24 (0x420000E0) /**< \brief (EVSYS) User Multiplexer 24 */
#define REG_EVSYS_USER25 (0x420000E4) /**< \brief (EVSYS) User Multiplexer 25 */
#define REG_EVSYS_USER26 (0x420000E8) /**< \brief (EVSYS) User Multiplexer 26 */
#define REG_EVSYS_USER27 (0x420000EC) /**< \brief (EVSYS) User Multiplexer 27 */
#define REG_EVSYS_USER28 (0x420000F0) /**< \brief (EVSYS) User Multiplexer 28 */
#define REG_EVSYS_USER29 (0x420000F4) /**< \brief (EVSYS) User Multiplexer 29 */
#define REG_EVSYS_USER30 (0x420000F8) /**< \brief (EVSYS) User Multiplexer 30 */
#define REG_EVSYS_USER31 (0x420000FC) /**< \brief (EVSYS) User Multiplexer 31 */
#define REG_EVSYS_USER32 (0x42000100) /**< \brief (EVSYS) User Multiplexer 32 */
#define REG_EVSYS_USER33 (0x42000104) /**< \brief (EVSYS) User Multiplexer 33 */
#define REG_EVSYS_USER34 (0x42000108) /**< \brief (EVSYS) User Multiplexer 34 */
#define REG_EVSYS_USER35 (0x4200010C) /**< \brief (EVSYS) User Multiplexer 35 */
#define REG_EVSYS_USER36 (0x42000110) /**< \brief (EVSYS) User Multiplexer 36 */
#define REG_EVSYS_USER37 (0x42000114) /**< \brief (EVSYS) User Multiplexer 37 */
#define REG_EVSYS_USER38 (0x42000118) /**< \brief (EVSYS) User Multiplexer 38 */
#define REG_EVSYS_USER39 (0x4200011C) /**< \brief (EVSYS) User Multiplexer 39 */
#define REG_EVSYS_USER40 (0x42000120) /**< \brief (EVSYS) User Multiplexer 40 */
#define REG_EVSYS_USER41 (0x42000124) /**< \brief (EVSYS) User Multiplexer 41 */
#define REG_EVSYS_USER42 (0x42000128) /**< \brief (EVSYS) User Multiplexer 42 */
#define REG_EVSYS_USER43 (0x4200012C) /**< \brief (EVSYS) User Multiplexer 43 */
#define REG_EVSYS_USER44 (0x42000130) /**< \brief (EVSYS) User Multiplexer 44 */
#define REG_EVSYS_USER45 (0x42000134) /**< \brief (EVSYS) User Multiplexer 45 */
#define REG_EVSYS_USER46 (0x42000138) /**< \brief (EVSYS) User Multiplexer 46 */
#else
#define REG_EVSYS_CTRLA (*(RwReg8 *)0x42000000UL) /**< \brief (EVSYS) Control */
#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200000CUL) /**< \brief (EVSYS) Channel Status */
#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000010UL) /**< \brief (EVSYS) Interrupt Enable Clear */
#define REG_EVSYS_INTENSET (*(RwReg *)0x42000014UL) /**< \brief (EVSYS) Interrupt Enable Set */
#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000018UL) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
#define REG_EVSYS_SWEVT (*(WoReg *)0x4200001CUL) /**< \brief (EVSYS) Software Event */
#define REG_EVSYS_CHANNEL0 (*(RwReg *)0x42000020UL) /**< \brief (EVSYS) Channel 0 */
#define REG_EVSYS_CHANNEL1 (*(RwReg *)0x42000024UL) /**< \brief (EVSYS) Channel 1 */
#define REG_EVSYS_CHANNEL2 (*(RwReg *)0x42000028UL) /**< \brief (EVSYS) Channel 2 */
#define REG_EVSYS_CHANNEL3 (*(RwReg *)0x4200002CUL) /**< \brief (EVSYS) Channel 3 */
#define REG_EVSYS_CHANNEL4 (*(RwReg *)0x42000030UL) /**< \brief (EVSYS) Channel 4 */
#define REG_EVSYS_CHANNEL5 (*(RwReg *)0x42000034UL) /**< \brief (EVSYS) Channel 5 */
#define REG_EVSYS_CHANNEL6 (*(RwReg *)0x42000038UL) /**< \brief (EVSYS) Channel 6 */
#define REG_EVSYS_CHANNEL7 (*(RwReg *)0x4200003CUL) /**< \brief (EVSYS) Channel 7 */
#define REG_EVSYS_CHANNEL8 (*(RwReg *)0x42000040UL) /**< \brief (EVSYS) Channel 8 */
#define REG_EVSYS_CHANNEL9 (*(RwReg *)0x42000044UL) /**< \brief (EVSYS) Channel 9 */
#define REG_EVSYS_CHANNEL10 (*(RwReg *)0x42000048UL) /**< \brief (EVSYS) Channel 10 */
#define REG_EVSYS_CHANNEL11 (*(RwReg *)0x4200004CUL) /**< \brief (EVSYS) Channel 11 */
#define REG_EVSYS_USER0 (*(RwReg *)0x42000080UL) /**< \brief (EVSYS) User Multiplexer 0 */
#define REG_EVSYS_USER1 (*(RwReg *)0x42000084UL) /**< \brief (EVSYS) User Multiplexer 1 */
#define REG_EVSYS_USER2 (*(RwReg *)0x42000088UL) /**< \brief (EVSYS) User Multiplexer 2 */
#define REG_EVSYS_USER3 (*(RwReg *)0x4200008CUL) /**< \brief (EVSYS) User Multiplexer 3 */
#define REG_EVSYS_USER4 (*(RwReg *)0x42000090UL) /**< \brief (EVSYS) User Multiplexer 4 */
#define REG_EVSYS_USER5 (*(RwReg *)0x42000094UL) /**< \brief (EVSYS) User Multiplexer 5 */
#define REG_EVSYS_USER6 (*(RwReg *)0x42000098UL) /**< \brief (EVSYS) User Multiplexer 6 */
#define REG_EVSYS_USER7 (*(RwReg *)0x4200009CUL) /**< \brief (EVSYS) User Multiplexer 7 */
#define REG_EVSYS_USER8 (*(RwReg *)0x420000A0UL) /**< \brief (EVSYS) User Multiplexer 8 */
#define REG_EVSYS_USER9 (*(RwReg *)0x420000A4UL) /**< \brief (EVSYS) User Multiplexer 9 */
#define REG_EVSYS_USER10 (*(RwReg *)0x420000A8UL) /**< \brief (EVSYS) User Multiplexer 10 */
#define REG_EVSYS_USER11 (*(RwReg *)0x420000ACUL) /**< \brief (EVSYS) User Multiplexer 11 */
#define REG_EVSYS_USER12 (*(RwReg *)0x420000B0UL) /**< \brief (EVSYS) User Multiplexer 12 */
#define REG_EVSYS_USER13 (*(RwReg *)0x420000B4UL) /**< \brief (EVSYS) User Multiplexer 13 */
#define REG_EVSYS_USER14 (*(RwReg *)0x420000B8UL) /**< \brief (EVSYS) User Multiplexer 14 */
#define REG_EVSYS_USER15 (*(RwReg *)0x420000BCUL) /**< \brief (EVSYS) User Multiplexer 15 */
#define REG_EVSYS_USER16 (*(RwReg *)0x420000C0UL) /**< \brief (EVSYS) User Multiplexer 16 */
#define REG_EVSYS_USER17 (*(RwReg *)0x420000C4UL) /**< \brief (EVSYS) User Multiplexer 17 */
#define REG_EVSYS_USER18 (*(RwReg *)0x420000C8UL) /**< \brief (EVSYS) User Multiplexer 18 */
#define REG_EVSYS_USER19 (*(RwReg *)0x420000CCUL) /**< \brief (EVSYS) User Multiplexer 19 */
#define REG_EVSYS_USER20 (*(RwReg *)0x420000D0UL) /**< \brief (EVSYS) User Multiplexer 20 */
#define REG_EVSYS_USER21 (*(RwReg *)0x420000D4UL) /**< \brief (EVSYS) User Multiplexer 21 */
#define REG_EVSYS_USER22 (*(RwReg *)0x420000D8UL) /**< \brief (EVSYS) User Multiplexer 22 */
#define REG_EVSYS_USER23 (*(RwReg *)0x420000DCUL) /**< \brief (EVSYS) User Multiplexer 23 */
#define REG_EVSYS_USER24 (*(RwReg *)0x420000E0UL) /**< \brief (EVSYS) User Multiplexer 24 */
#define REG_EVSYS_USER25 (*(RwReg *)0x420000E4UL) /**< \brief (EVSYS) User Multiplexer 25 */
#define REG_EVSYS_USER26 (*(RwReg *)0x420000E8UL) /**< \brief (EVSYS) User Multiplexer 26 */
#define REG_EVSYS_USER27 (*(RwReg *)0x420000ECUL) /**< \brief (EVSYS) User Multiplexer 27 */
#define REG_EVSYS_USER28 (*(RwReg *)0x420000F0UL) /**< \brief (EVSYS) User Multiplexer 28 */
#define REG_EVSYS_USER29 (*(RwReg *)0x420000F4UL) /**< \brief (EVSYS) User Multiplexer 29 */
#define REG_EVSYS_USER30 (*(RwReg *)0x420000F8UL) /**< \brief (EVSYS) User Multiplexer 30 */
#define REG_EVSYS_USER31 (*(RwReg *)0x420000FCUL) /**< \brief (EVSYS) User Multiplexer 31 */
#define REG_EVSYS_USER32 (*(RwReg *)0x42000100UL) /**< \brief (EVSYS) User Multiplexer 32 */
#define REG_EVSYS_USER33 (*(RwReg *)0x42000104UL) /**< \brief (EVSYS) User Multiplexer 33 */
#define REG_EVSYS_USER34 (*(RwReg *)0x42000108UL) /**< \brief (EVSYS) User Multiplexer 34 */
#define REG_EVSYS_USER35 (*(RwReg *)0x4200010CUL) /**< \brief (EVSYS) User Multiplexer 35 */
#define REG_EVSYS_USER36 (*(RwReg *)0x42000110UL) /**< \brief (EVSYS) User Multiplexer 36 */
#define REG_EVSYS_USER37 (*(RwReg *)0x42000114UL) /**< \brief (EVSYS) User Multiplexer 37 */
#define REG_EVSYS_USER38 (*(RwReg *)0x42000118UL) /**< \brief (EVSYS) User Multiplexer 38 */
#define REG_EVSYS_USER39 (*(RwReg *)0x4200011CUL) /**< \brief (EVSYS) User Multiplexer 39 */
#define REG_EVSYS_USER40 (*(RwReg *)0x42000120UL) /**< \brief (EVSYS) User Multiplexer 40 */
#define REG_EVSYS_USER41 (*(RwReg *)0x42000124UL) /**< \brief (EVSYS) User Multiplexer 41 */
#define REG_EVSYS_USER42 (*(RwReg *)0x42000128UL) /**< \brief (EVSYS) User Multiplexer 42 */
#define REG_EVSYS_USER43 (*(RwReg *)0x4200012CUL) /**< \brief (EVSYS) User Multiplexer 43 */
#define REG_EVSYS_USER44 (*(RwReg *)0x42000130UL) /**< \brief (EVSYS) User Multiplexer 44 */
#define REG_EVSYS_USER45 (*(RwReg *)0x42000134UL) /**< \brief (EVSYS) User Multiplexer 45 */
#define REG_EVSYS_USER46 (*(RwReg *)0x42000138UL) /**< \brief (EVSYS) User Multiplexer 46 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for EVSYS peripheral ========== */
#define EVSYS_CHANNELS_BITS 4 // Number of bits to select Channel
#define EVSYS_CHANNELS_MSB 11 // Number of Channels - 1
#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators
#define EVSYS_GCLK_ID_0 6
#define EVSYS_GCLK_ID_1 7
#define EVSYS_GCLK_ID_2 8
#define EVSYS_GCLK_ID_3 9
#define EVSYS_GCLK_ID_4 10
#define EVSYS_GCLK_ID_5 11
#define EVSYS_GCLK_ID_6 12
#define EVSYS_GCLK_ID_7 13
#define EVSYS_GCLK_ID_8 14
#define EVSYS_GCLK_ID_9 15
#define EVSYS_GCLK_ID_10 16
#define EVSYS_GCLK_ID_11 17
#define EVSYS_GCLK_ID_LSB 6
#define EVSYS_GCLK_ID_MSB 17
#define EVSYS_GCLK_ID_SIZE 12
#define EVSYS_GENERATORS 87 // Total Number of Event Generators
#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator
#define EVSYS_USERS 47 // Total Number of Event Users
#define EVSYS_USERS_BITS 6 // Number of bits to select Event User
// GENERATORS
#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL 1
#define EVSYS_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 2
#define EVSYS_ID_GEN_RTC_CMP_0 3
#define EVSYS_ID_GEN_RTC_CMP_1 4
#define EVSYS_ID_GEN_RTC_OVF 5
#define EVSYS_ID_GEN_RTC_PER_0 6
#define EVSYS_ID_GEN_RTC_PER_1 7
#define EVSYS_ID_GEN_RTC_PER_2 8
#define EVSYS_ID_GEN_RTC_PER_3 9
#define EVSYS_ID_GEN_RTC_PER_4 10
#define EVSYS_ID_GEN_RTC_PER_5 11
#define EVSYS_ID_GEN_RTC_PER_6 12
#define EVSYS_ID_GEN_RTC_PER_7 13
#define EVSYS_ID_GEN_EIC_EXTINT_0 14
#define EVSYS_ID_GEN_EIC_EXTINT_1 15
#define EVSYS_ID_GEN_EIC_EXTINT_2 16
#define EVSYS_ID_GEN_EIC_EXTINT_3 17
#define EVSYS_ID_GEN_EIC_EXTINT_4 18
#define EVSYS_ID_GEN_EIC_EXTINT_5 19
#define EVSYS_ID_GEN_EIC_EXTINT_6 20
#define EVSYS_ID_GEN_EIC_EXTINT_7 21
#define EVSYS_ID_GEN_EIC_EXTINT_8 22
#define EVSYS_ID_GEN_EIC_EXTINT_9 23
#define EVSYS_ID_GEN_EIC_EXTINT_10 24
#define EVSYS_ID_GEN_EIC_EXTINT_11 25
#define EVSYS_ID_GEN_EIC_EXTINT_12 26
#define EVSYS_ID_GEN_EIC_EXTINT_13 27
#define EVSYS_ID_GEN_EIC_EXTINT_14 28
#define EVSYS_ID_GEN_EIC_EXTINT_15 29
#define EVSYS_ID_GEN_TSENS_WINMON 30
#define EVSYS_ID_GEN_DMAC_CH_0 31
#define EVSYS_ID_GEN_DMAC_CH_1 32
#define EVSYS_ID_GEN_DMAC_CH_2 33
#define EVSYS_ID_GEN_DMAC_CH_3 34
#define EVSYS_ID_GEN_TCC0_OVF 35
#define EVSYS_ID_GEN_TCC0_TRG 36
#define EVSYS_ID_GEN_TCC0_CNT 37
#define EVSYS_ID_GEN_TCC0_MCX_0 38
#define EVSYS_ID_GEN_TCC0_MCX_1 39
#define EVSYS_ID_GEN_TCC0_MCX_2 40
#define EVSYS_ID_GEN_TCC0_MCX_3 41
#define EVSYS_ID_GEN_TCC1_OVF 42
#define EVSYS_ID_GEN_TCC1_TRG 43
#define EVSYS_ID_GEN_TCC1_CNT 44
#define EVSYS_ID_GEN_TCC1_MCX_0 45
#define EVSYS_ID_GEN_TCC1_MCX_1 46
#define EVSYS_ID_GEN_TCC2_OVF 47
#define EVSYS_ID_GEN_TCC2_TRG 48
#define EVSYS_ID_GEN_TCC2_CNT 49
#define EVSYS_ID_GEN_TCC2_MCX_0 50
#define EVSYS_ID_GEN_TCC2_MCX_1 51
#define EVSYS_ID_GEN_TC0_OVF 52
#define EVSYS_ID_GEN_TC0_MCX_0 53
#define EVSYS_ID_GEN_TC0_MCX_1 54
#define EVSYS_ID_GEN_TC1_OVF 55
#define EVSYS_ID_GEN_TC1_MCX_0 56
#define EVSYS_ID_GEN_TC1_MCX_1 57
#define EVSYS_ID_GEN_TC2_OVF 58
#define EVSYS_ID_GEN_TC2_MCX_0 59
#define EVSYS_ID_GEN_TC2_MCX_1 60
#define EVSYS_ID_GEN_TC3_OVF 61
#define EVSYS_ID_GEN_TC3_MCX_0 62
#define EVSYS_ID_GEN_TC3_MCX_1 63
#define EVSYS_ID_GEN_TC4_OVF 64
#define EVSYS_ID_GEN_TC4_MCX_0 65
#define EVSYS_ID_GEN_TC4_MCX_1 66
#define EVSYS_ID_GEN_ADC0_RESRDY 67
#define EVSYS_ID_GEN_ADC0_WINMON 68
#define EVSYS_ID_GEN_ADC1_RESRDY 69
#define EVSYS_ID_GEN_ADC1_WINMON 70
#define EVSYS_ID_GEN_SDADC_RESRDY 71
#define EVSYS_ID_GEN_SDADC_WINMON 72
#define EVSYS_ID_GEN_AC_COMP_0 73
#define EVSYS_ID_GEN_AC_COMP_1 74
#define EVSYS_ID_GEN_AC_COMP_2 75
#define EVSYS_ID_GEN_AC_COMP_3 76
#define EVSYS_ID_GEN_AC_WIN_0 77
#define EVSYS_ID_GEN_AC_WIN_1 78
#define EVSYS_ID_GEN_DAC_EMPTY 79
#define EVSYS_ID_GEN_CCL_LUTOUT_0 82
#define EVSYS_ID_GEN_CCL_LUTOUT_1 83
#define EVSYS_ID_GEN_CCL_LUTOUT_2 84
#define EVSYS_ID_GEN_CCL_LUTOUT_3 85
#define EVSYS_ID_GEN_PAC_ACCERR 86
// USERS
#define EVSYS_ID_USER_TSENS_START 0
#define EVSYS_ID_USER_PORT_EV_0 1
#define EVSYS_ID_USER_PORT_EV_1 2
#define EVSYS_ID_USER_PORT_EV_2 3
#define EVSYS_ID_USER_PORT_EV_3 4
#define EVSYS_ID_USER_DMAC_CH_0 5
#define EVSYS_ID_USER_DMAC_CH_1 6
#define EVSYS_ID_USER_DMAC_CH_2 7
#define EVSYS_ID_USER_DMAC_CH_3 8
#define EVSYS_ID_USER_TCC0_EV_0 9
#define EVSYS_ID_USER_TCC0_EV_1 10
#define EVSYS_ID_USER_TCC0_MC_0 11
#define EVSYS_ID_USER_TCC0_MC_1 12
#define EVSYS_ID_USER_TCC0_MC_2 13
#define EVSYS_ID_USER_TCC0_MC_3 14
#define EVSYS_ID_USER_TCC1_EV_0 15
#define EVSYS_ID_USER_TCC1_EV_1 16
#define EVSYS_ID_USER_TCC1_MC_0 17
#define EVSYS_ID_USER_TCC1_MC_1 18
#define EVSYS_ID_USER_TCC2_EV_0 19
#define EVSYS_ID_USER_TCC2_EV_1 20
#define EVSYS_ID_USER_TCC2_MC_0 21
#define EVSYS_ID_USER_TCC2_MC_1 22
#define EVSYS_ID_USER_TC0_EVU 23
#define EVSYS_ID_USER_TC1_EVU 24
#define EVSYS_ID_USER_TC2_EVU 25
#define EVSYS_ID_USER_TC3_EVU 26
#define EVSYS_ID_USER_TC4_EVU 27
#define EVSYS_ID_USER_ADC0_START 28
#define EVSYS_ID_USER_ADC0_SYNC 29
#define EVSYS_ID_USER_ADC1_START 30
#define EVSYS_ID_USER_ADC1_SYNC 31
#define EVSYS_ID_USER_SDADC_START 32
#define EVSYS_ID_USER_SDADC_FLUSH 33
#define EVSYS_ID_USER_AC_SOC_0 34
#define EVSYS_ID_USER_AC_SOC_1 35
#define EVSYS_ID_USER_AC_SOC_2 36
#define EVSYS_ID_USER_AC_SOC_3 37
#define EVSYS_ID_USER_DAC_START 38
#define EVSYS_ID_USER_CCL_LUTIN_0 40
#define EVSYS_ID_USER_CCL_LUTIN_1 41
#define EVSYS_ID_USER_CCL_LUTIN_2 42
#define EVSYS_ID_USER_CCL_LUTIN_3 43
#define EVSYS_ID_USER_MTB_START 45
#define EVSYS_ID_USER_MTB_STOP 46
#endif /* _SAMC21_EVSYS_INSTANCE_ */

60
lib/samc21/samc21/include/instance/freqm.h Normal file
View File

@@ -0,0 +1,60 @@
/**
* \file
*
* \brief Instance description for FREQM
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_FREQM_INSTANCE_
#define _SAMC21_FREQM_INSTANCE_
/* ========== Register definition for FREQM peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_FREQM_CTRLA (0x40002C00) /**< \brief (FREQM) Control A Register */
#define REG_FREQM_CTRLB (0x40002C01) /**< \brief (FREQM) Control B Register */
#define REG_FREQM_CFGA (0x40002C02) /**< \brief (FREQM) Config A register */
#define REG_FREQM_INTENCLR (0x40002C08) /**< \brief (FREQM) Interrupt Enable Clear Register */
#define REG_FREQM_INTENSET (0x40002C09) /**< \brief (FREQM) Interrupt Enable Set Register */
#define REG_FREQM_INTFLAG (0x40002C0A) /**< \brief (FREQM) Interrupt Flag Register */
#define REG_FREQM_STATUS (0x40002C0B) /**< \brief (FREQM) Status Register */
#define REG_FREQM_SYNCBUSY (0x40002C0C) /**< \brief (FREQM) Synchronization Busy Register */
#define REG_FREQM_VALUE (0x40002C10) /**< \brief (FREQM) Count Value Register */
#else
#define REG_FREQM_CTRLA (*(RwReg8 *)0x40002C00UL) /**< \brief (FREQM) Control A Register */
#define REG_FREQM_CTRLB (*(WoReg8 *)0x40002C01UL) /**< \brief (FREQM) Control B Register */
#define REG_FREQM_CFGA (*(RwReg16*)0x40002C02UL) /**< \brief (FREQM) Config A register */
#define REG_FREQM_INTENCLR (*(RwReg8 *)0x40002C08UL) /**< \brief (FREQM) Interrupt Enable Clear Register */
#define REG_FREQM_INTENSET (*(RwReg8 *)0x40002C09UL) /**< \brief (FREQM) Interrupt Enable Set Register */
#define REG_FREQM_INTFLAG (*(RwReg8 *)0x40002C0AUL) /**< \brief (FREQM) Interrupt Flag Register */
#define REG_FREQM_STATUS (*(RwReg8 *)0x40002C0BUL) /**< \brief (FREQM) Status Register */
#define REG_FREQM_SYNCBUSY (*(RoReg *)0x40002C0CUL) /**< \brief (FREQM) Synchronization Busy Register */
#define REG_FREQM_VALUE (*(RoReg *)0x40002C10UL) /**< \brief (FREQM) Count Value Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for FREQM peripheral ========== */
#define FREQM_GCLK_ID_MSR 3 // Index of measure generic clock
#define FREQM_GCLK_ID_REF 4 // Index of reference generic clock
#endif /* _SAMC21_FREQM_INSTANCE_ */

160
lib/samc21/samc21/include/instance/gclk.h Normal file
View File

@@ -0,0 +1,160 @@
/**
* \file
*
* \brief Instance description for GCLK
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_GCLK_INSTANCE_
#define _SAMC21_GCLK_INSTANCE_
/* ========== Register definition for GCLK peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_GCLK_CTRLA (0x40001C00) /**< \brief (GCLK) Control */
#define REG_GCLK_SYNCBUSY (0x40001C04) /**< \brief (GCLK) Synchronization Busy */
#define REG_GCLK_GENCTRL0 (0x40001C20) /**< \brief (GCLK) Generic Clock Generator Control 0 */
#define REG_GCLK_GENCTRL1 (0x40001C24) /**< \brief (GCLK) Generic Clock Generator Control 1 */
#define REG_GCLK_GENCTRL2 (0x40001C28) /**< \brief (GCLK) Generic Clock Generator Control 2 */
#define REG_GCLK_GENCTRL3 (0x40001C2C) /**< \brief (GCLK) Generic Clock Generator Control 3 */
#define REG_GCLK_GENCTRL4 (0x40001C30) /**< \brief (GCLK) Generic Clock Generator Control 4 */
#define REG_GCLK_GENCTRL5 (0x40001C34) /**< \brief (GCLK) Generic Clock Generator Control 5 */
#define REG_GCLK_GENCTRL6 (0x40001C38) /**< \brief (GCLK) Generic Clock Generator Control 6 */
#define REG_GCLK_GENCTRL7 (0x40001C3C) /**< \brief (GCLK) Generic Clock Generator Control 7 */
#define REG_GCLK_GENCTRL8 (0x40001C40) /**< \brief (GCLK) Generic Clock Generator Control 8 */
#define REG_GCLK_PCHCTRL0 (0x40001C80) /**< \brief (GCLK) Peripheral Clock Control 0 */
#define REG_GCLK_PCHCTRL1 (0x40001C84) /**< \brief (GCLK) Peripheral Clock Control 1 */
#define REG_GCLK_PCHCTRL2 (0x40001C88) /**< \brief (GCLK) Peripheral Clock Control 2 */
#define REG_GCLK_PCHCTRL3 (0x40001C8C) /**< \brief (GCLK) Peripheral Clock Control 3 */
#define REG_GCLK_PCHCTRL4 (0x40001C90) /**< \brief (GCLK) Peripheral Clock Control 4 */
#define REG_GCLK_PCHCTRL5 (0x40001C94) /**< \brief (GCLK) Peripheral Clock Control 5 */
#define REG_GCLK_PCHCTRL6 (0x40001C98) /**< \brief (GCLK) Peripheral Clock Control 6 */
#define REG_GCLK_PCHCTRL7 (0x40001C9C) /**< \brief (GCLK) Peripheral Clock Control 7 */
#define REG_GCLK_PCHCTRL8 (0x40001CA0) /**< \brief (GCLK) Peripheral Clock Control 8 */
#define REG_GCLK_PCHCTRL9 (0x40001CA4) /**< \brief (GCLK) Peripheral Clock Control 9 */
#define REG_GCLK_PCHCTRL10 (0x40001CA8) /**< \brief (GCLK) Peripheral Clock Control 10 */
#define REG_GCLK_PCHCTRL11 (0x40001CAC) /**< \brief (GCLK) Peripheral Clock Control 11 */
#define REG_GCLK_PCHCTRL12 (0x40001CB0) /**< \brief (GCLK) Peripheral Clock Control 12 */
#define REG_GCLK_PCHCTRL13 (0x40001CB4) /**< \brief (GCLK) Peripheral Clock Control 13 */
#define REG_GCLK_PCHCTRL14 (0x40001CB8) /**< \brief (GCLK) Peripheral Clock Control 14 */
#define REG_GCLK_PCHCTRL15 (0x40001CBC) /**< \brief (GCLK) Peripheral Clock Control 15 */
#define REG_GCLK_PCHCTRL16 (0x40001CC0) /**< \brief (GCLK) Peripheral Clock Control 16 */
#define REG_GCLK_PCHCTRL17 (0x40001CC4) /**< \brief (GCLK) Peripheral Clock Control 17 */
#define REG_GCLK_PCHCTRL18 (0x40001CC8) /**< \brief (GCLK) Peripheral Clock Control 18 */
#define REG_GCLK_PCHCTRL19 (0x40001CCC) /**< \brief (GCLK) Peripheral Clock Control 19 */
#define REG_GCLK_PCHCTRL20 (0x40001CD0) /**< \brief (GCLK) Peripheral Clock Control 20 */
#define REG_GCLK_PCHCTRL21 (0x40001CD4) /**< \brief (GCLK) Peripheral Clock Control 21 */
#define REG_GCLK_PCHCTRL22 (0x40001CD8) /**< \brief (GCLK) Peripheral Clock Control 22 */
#define REG_GCLK_PCHCTRL23 (0x40001CDC) /**< \brief (GCLK) Peripheral Clock Control 23 */
#define REG_GCLK_PCHCTRL24 (0x40001CE0) /**< \brief (GCLK) Peripheral Clock Control 24 */
#define REG_GCLK_PCHCTRL25 (0x40001CE4) /**< \brief (GCLK) Peripheral Clock Control 25 */
#define REG_GCLK_PCHCTRL26 (0x40001CE8) /**< \brief (GCLK) Peripheral Clock Control 26 */
#define REG_GCLK_PCHCTRL27 (0x40001CEC) /**< \brief (GCLK) Peripheral Clock Control 27 */
#define REG_GCLK_PCHCTRL28 (0x40001CF0) /**< \brief (GCLK) Peripheral Clock Control 28 */
#define REG_GCLK_PCHCTRL29 (0x40001CF4) /**< \brief (GCLK) Peripheral Clock Control 29 */
#define REG_GCLK_PCHCTRL30 (0x40001CF8) /**< \brief (GCLK) Peripheral Clock Control 30 */
#define REG_GCLK_PCHCTRL31 (0x40001CFC) /**< \brief (GCLK) Peripheral Clock Control 31 */
#define REG_GCLK_PCHCTRL32 (0x40001D00) /**< \brief (GCLK) Peripheral Clock Control 32 */
#define REG_GCLK_PCHCTRL33 (0x40001D04) /**< \brief (GCLK) Peripheral Clock Control 33 */
#define REG_GCLK_PCHCTRL34 (0x40001D08) /**< \brief (GCLK) Peripheral Clock Control 34 */
#define REG_GCLK_PCHCTRL35 (0x40001D0C) /**< \brief (GCLK) Peripheral Clock Control 35 */
#define REG_GCLK_PCHCTRL36 (0x40001D10) /**< \brief (GCLK) Peripheral Clock Control 36 */
#define REG_GCLK_PCHCTRL37 (0x40001D14) /**< \brief (GCLK) Peripheral Clock Control 37 */
#define REG_GCLK_PCHCTRL38 (0x40001D18) /**< \brief (GCLK) Peripheral Clock Control 38 */
#define REG_GCLK_PCHCTRL39 (0x40001D1C) /**< \brief (GCLK) Peripheral Clock Control 39 */
#define REG_GCLK_PCHCTRL40 (0x40001D20) /**< \brief (GCLK) Peripheral Clock Control 40 */
#else
#define REG_GCLK_CTRLA (*(RwReg8 *)0x40001C00UL) /**< \brief (GCLK) Control */
#define REG_GCLK_SYNCBUSY (*(RoReg *)0x40001C04UL) /**< \brief (GCLK) Synchronization Busy */
#define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001C20UL) /**< \brief (GCLK) Generic Clock Generator Control 0 */
#define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001C24UL) /**< \brief (GCLK) Generic Clock Generator Control 1 */
#define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001C28UL) /**< \brief (GCLK) Generic Clock Generator Control 2 */
#define REG_GCLK_GENCTRL3 (*(RwReg *)0x40001C2CUL) /**< \brief (GCLK) Generic Clock Generator Control 3 */
#define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001C30UL) /**< \brief (GCLK) Generic Clock Generator Control 4 */
#define REG_GCLK_GENCTRL5 (*(RwReg *)0x40001C34UL) /**< \brief (GCLK) Generic Clock Generator Control 5 */
#define REG_GCLK_GENCTRL6 (*(RwReg *)0x40001C38UL) /**< \brief (GCLK) Generic Clock Generator Control 6 */
#define REG_GCLK_GENCTRL7 (*(RwReg *)0x40001C3CUL) /**< \brief (GCLK) Generic Clock Generator Control 7 */
#define REG_GCLK_GENCTRL8 (*(RwReg *)0x40001C40UL) /**< \brief (GCLK) Generic Clock Generator Control 8 */
#define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001C80UL) /**< \brief (GCLK) Peripheral Clock Control 0 */
#define REG_GCLK_PCHCTRL1 (*(RwReg *)0x40001C84UL) /**< \brief (GCLK) Peripheral Clock Control 1 */
#define REG_GCLK_PCHCTRL2 (*(RwReg *)0x40001C88UL) /**< \brief (GCLK) Peripheral Clock Control 2 */
#define REG_GCLK_PCHCTRL3 (*(RwReg *)0x40001C8CUL) /**< \brief (GCLK) Peripheral Clock Control 3 */
#define REG_GCLK_PCHCTRL4 (*(RwReg *)0x40001C90UL) /**< \brief (GCLK) Peripheral Clock Control 4 */
#define REG_GCLK_PCHCTRL5 (*(RwReg *)0x40001C94UL) /**< \brief (GCLK) Peripheral Clock Control 5 */
#define REG_GCLK_PCHCTRL6 (*(RwReg *)0x40001C98UL) /**< \brief (GCLK) Peripheral Clock Control 6 */
#define REG_GCLK_PCHCTRL7 (*(RwReg *)0x40001C9CUL) /**< \brief (GCLK) Peripheral Clock Control 7 */
#define REG_GCLK_PCHCTRL8 (*(RwReg *)0x40001CA0UL) /**< \brief (GCLK) Peripheral Clock Control 8 */
#define REG_GCLK_PCHCTRL9 (*(RwReg *)0x40001CA4UL) /**< \brief (GCLK) Peripheral Clock Control 9 */
#define REG_GCLK_PCHCTRL10 (*(RwReg *)0x40001CA8UL) /**< \brief (GCLK) Peripheral Clock Control 10 */
#define REG_GCLK_PCHCTRL11 (*(RwReg *)0x40001CACUL) /**< \brief (GCLK) Peripheral Clock Control 11 */
#define REG_GCLK_PCHCTRL12 (*(RwReg *)0x40001CB0UL) /**< \brief (GCLK) Peripheral Clock Control 12 */
#define REG_GCLK_PCHCTRL13 (*(RwReg *)0x40001CB4UL) /**< \brief (GCLK) Peripheral Clock Control 13 */
#define REG_GCLK_PCHCTRL14 (*(RwReg *)0x40001CB8UL) /**< \brief (GCLK) Peripheral Clock Control 14 */
#define REG_GCLK_PCHCTRL15 (*(RwReg *)0x40001CBCUL) /**< \brief (GCLK) Peripheral Clock Control 15 */
#define REG_GCLK_PCHCTRL16 (*(RwReg *)0x40001CC0UL) /**< \brief (GCLK) Peripheral Clock Control 16 */
#define REG_GCLK_PCHCTRL17 (*(RwReg *)0x40001CC4UL) /**< \brief (GCLK) Peripheral Clock Control 17 */
#define REG_GCLK_PCHCTRL18 (*(RwReg *)0x40001CC8UL) /**< \brief (GCLK) Peripheral Clock Control 18 */
#define REG_GCLK_PCHCTRL19 (*(RwReg *)0x40001CCCUL) /**< \brief (GCLK) Peripheral Clock Control 19 */
#define REG_GCLK_PCHCTRL20 (*(RwReg *)0x40001CD0UL) /**< \brief (GCLK) Peripheral Clock Control 20 */
#define REG_GCLK_PCHCTRL21 (*(RwReg *)0x40001CD4UL) /**< \brief (GCLK) Peripheral Clock Control 21 */
#define REG_GCLK_PCHCTRL22 (*(RwReg *)0x40001CD8UL) /**< \brief (GCLK) Peripheral Clock Control 22 */
#define REG_GCLK_PCHCTRL23 (*(RwReg *)0x40001CDCUL) /**< \brief (GCLK) Peripheral Clock Control 23 */
#define REG_GCLK_PCHCTRL24 (*(RwReg *)0x40001CE0UL) /**< \brief (GCLK) Peripheral Clock Control 24 */
#define REG_GCLK_PCHCTRL25 (*(RwReg *)0x40001CE4UL) /**< \brief (GCLK) Peripheral Clock Control 25 */
#define REG_GCLK_PCHCTRL26 (*(RwReg *)0x40001CE8UL) /**< \brief (GCLK) Peripheral Clock Control 26 */
#define REG_GCLK_PCHCTRL27 (*(RwReg *)0x40001CECUL) /**< \brief (GCLK) Peripheral Clock Control 27 */
#define REG_GCLK_PCHCTRL28 (*(RwReg *)0x40001CF0UL) /**< \brief (GCLK) Peripheral Clock Control 28 */
#define REG_GCLK_PCHCTRL29 (*(RwReg *)0x40001CF4UL) /**< \brief (GCLK) Peripheral Clock Control 29 */
#define REG_GCLK_PCHCTRL30 (*(RwReg *)0x40001CF8UL) /**< \brief (GCLK) Peripheral Clock Control 30 */
#define REG_GCLK_PCHCTRL31 (*(RwReg *)0x40001CFCUL) /**< \brief (GCLK) Peripheral Clock Control 31 */
#define REG_GCLK_PCHCTRL32 (*(RwReg *)0x40001D00UL) /**< \brief (GCLK) Peripheral Clock Control 32 */
#define REG_GCLK_PCHCTRL33 (*(RwReg *)0x40001D04UL) /**< \brief (GCLK) Peripheral Clock Control 33 */
#define REG_GCLK_PCHCTRL34 (*(RwReg *)0x40001D08UL) /**< \brief (GCLK) Peripheral Clock Control 34 */
#define REG_GCLK_PCHCTRL35 (*(RwReg *)0x40001D0CUL) /**< \brief (GCLK) Peripheral Clock Control 35 */
#define REG_GCLK_PCHCTRL36 (*(RwReg *)0x40001D10UL) /**< \brief (GCLK) Peripheral Clock Control 36 */
#define REG_GCLK_PCHCTRL37 (*(RwReg *)0x40001D14UL) /**< \brief (GCLK) Peripheral Clock Control 37 */
#define REG_GCLK_PCHCTRL38 (*(RwReg *)0x40001D18UL) /**< \brief (GCLK) Peripheral Clock Control 38 */
#define REG_GCLK_PCHCTRL39 (*(RwReg *)0x40001D1CUL) /**< \brief (GCLK) Peripheral Clock Control 39 */
#define REG_GCLK_PCHCTRL40 (*(RwReg *)0x40001D20UL) /**< \brief (GCLK) Peripheral Clock Control 40 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for GCLK peripheral ========== */
#define GCLK_GENDIV_BITS 16
#define GCLK_GEN_BITS 4
#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
#define GCLK_GEN_SOURCE_NUM_MSB 7 // Number of Generic Clock Sources - 1
#define GCLK_NUM 41 // Number of Generic Clock Users
#define GCLK_SOURCE_BITS 3
#define GCLK_SOURCE_DPLL96M 7
#define GCLK_SOURCE_GCLKGEN1 2
#define GCLK_SOURCE_GCLKIN 1
#define GCLK_SOURCE_NUM 8 // Number of Generic Clock Sources
#define GCLK_SOURCE_OSCULP32K 3
#define GCLK_SOURCE_OSC32K 4
#define GCLK_SOURCE_OSC48M 6
#define GCLK_SOURCE_XOSC 0
#define GCLK_SOURCE_XOSC32K 5
#endif /* _SAMC21_GCLK_INSTANCE_ */

156
lib/samc21/samc21/include/instance/hmatrixhs.h Normal file
View File

@@ -0,0 +1,156 @@
/**
* \file
*
* \brief Instance description for HMATRIXHS
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_HMATRIXHS_INSTANCE_
#define _SAMC21_HMATRIXHS_INSTANCE_
/* ========== Register definition for HMATRIXHS peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_HMATRIXHS_MCFG0 (0x4100A000) /**< \brief (HMATRIXHS) Master Configuration 0 */
#define REG_HMATRIXHS_MCFG1 (0x4100A004) /**< \brief (HMATRIXHS) Master Configuration 1 */
#define REG_HMATRIXHS_MCFG2 (0x4100A008) /**< \brief (HMATRIXHS) Master Configuration 2 */
#define REG_HMATRIXHS_MCFG3 (0x4100A00C) /**< \brief (HMATRIXHS) Master Configuration 3 */
#define REG_HMATRIXHS_MCFG4 (0x4100A010) /**< \brief (HMATRIXHS) Master Configuration 4 */
#define REG_HMATRIXHS_MCFG5 (0x4100A014) /**< \brief (HMATRIXHS) Master Configuration 5 */
#define REG_HMATRIXHS_MCFG6 (0x4100A018) /**< \brief (HMATRIXHS) Master Configuration 6 */
#define REG_HMATRIXHS_MCFG7 (0x4100A01C) /**< \brief (HMATRIXHS) Master Configuration 7 */
#define REG_HMATRIXHS_MCFG8 (0x4100A020) /**< \brief (HMATRIXHS) Master Configuration 8 */
#define REG_HMATRIXHS_MCFG9 (0x4100A024) /**< \brief (HMATRIXHS) Master Configuration 9 */
#define REG_HMATRIXHS_MCFG10 (0x4100A028) /**< \brief (HMATRIXHS) Master Configuration 10 */
#define REG_HMATRIXHS_MCFG11 (0x4100A02C) /**< \brief (HMATRIXHS) Master Configuration 11 */
#define REG_HMATRIXHS_MCFG12 (0x4100A030) /**< \brief (HMATRIXHS) Master Configuration 12 */
#define REG_HMATRIXHS_MCFG13 (0x4100A034) /**< \brief (HMATRIXHS) Master Configuration 13 */
#define REG_HMATRIXHS_MCFG14 (0x4100A038) /**< \brief (HMATRIXHS) Master Configuration 14 */
#define REG_HMATRIXHS_MCFG15 (0x4100A03C) /**< \brief (HMATRIXHS) Master Configuration 15 */
#define REG_HMATRIXHS_SCFG0 (0x4100A040) /**< \brief (HMATRIXHS) Slave Configuration 0 */
#define REG_HMATRIXHS_SCFG1 (0x4100A044) /**< \brief (HMATRIXHS) Slave Configuration 1 */
#define REG_HMATRIXHS_SCFG2 (0x4100A048) /**< \brief (HMATRIXHS) Slave Configuration 2 */
#define REG_HMATRIXHS_SCFG3 (0x4100A04C) /**< \brief (HMATRIXHS) Slave Configuration 3 */
#define REG_HMATRIXHS_SCFG4 (0x4100A050) /**< \brief (HMATRIXHS) Slave Configuration 4 */
#define REG_HMATRIXHS_SCFG5 (0x4100A054) /**< \brief (HMATRIXHS) Slave Configuration 5 */
#define REG_HMATRIXHS_SCFG6 (0x4100A058) /**< \brief (HMATRIXHS) Slave Configuration 6 */
#define REG_HMATRIXHS_SCFG7 (0x4100A05C) /**< \brief (HMATRIXHS) Slave Configuration 7 */
#define REG_HMATRIXHS_SCFG8 (0x4100A060) /**< \brief (HMATRIXHS) Slave Configuration 8 */
#define REG_HMATRIXHS_SCFG9 (0x4100A064) /**< \brief (HMATRIXHS) Slave Configuration 9 */
#define REG_HMATRIXHS_SCFG10 (0x4100A068) /**< \brief (HMATRIXHS) Slave Configuration 10 */
#define REG_HMATRIXHS_SCFG11 (0x4100A06C) /**< \brief (HMATRIXHS) Slave Configuration 11 */
#define REG_HMATRIXHS_SCFG12 (0x4100A070) /**< \brief (HMATRIXHS) Slave Configuration 12 */
#define REG_HMATRIXHS_SCFG13 (0x4100A074) /**< \brief (HMATRIXHS) Slave Configuration 13 */
#define REG_HMATRIXHS_SCFG14 (0x4100A078) /**< \brief (HMATRIXHS) Slave Configuration 14 */
#define REG_HMATRIXHS_SCFG15 (0x4100A07C) /**< \brief (HMATRIXHS) Slave Configuration 15 */
#define REG_HMATRIXHS_PRAS0 (0x4100A080) /**< \brief (HMATRIXHS) Priority A for Slave 0 */
#define REG_HMATRIXHS_PRBS0 (0x4100A084) /**< \brief (HMATRIXHS) Priority B for Slave 0 */
#define REG_HMATRIXHS_PRAS1 (0x4100A088) /**< \brief (HMATRIXHS) Priority A for Slave 1 */
#define REG_HMATRIXHS_PRBS1 (0x4100A08C) /**< \brief (HMATRIXHS) Priority B for Slave 1 */
#define REG_HMATRIXHS_PRAS2 (0x4100A090) /**< \brief (HMATRIXHS) Priority A for Slave 2 */
#define REG_HMATRIXHS_PRBS2 (0x4100A094) /**< \brief (HMATRIXHS) Priority B for Slave 2 */
#define REG_HMATRIXHS_PRAS3 (0x4100A098) /**< \brief (HMATRIXHS) Priority A for Slave 3 */
#define REG_HMATRIXHS_PRBS3 (0x4100A09C) /**< \brief (HMATRIXHS) Priority B for Slave 3 */
#define REG_HMATRIXHS_MRCR (0x4100A100) /**< \brief (HMATRIXHS) Master Remap Control */
#define REG_HMATRIXHS_SFR0 (0x4100A110) /**< \brief (HMATRIXHS) Special Function 0 */
#define REG_HMATRIXHS_SFR1 (0x4100A114) /**< \brief (HMATRIXHS) Special Function 1 */
#define REG_HMATRIXHS_SFR2 (0x4100A118) /**< \brief (HMATRIXHS) Special Function 2 */
#define REG_HMATRIXHS_SFR3 (0x4100A11C) /**< \brief (HMATRIXHS) Special Function 3 */
#define REG_HMATRIXHS_SFR4 (0x4100A120) /**< \brief (HMATRIXHS) Special Function 4 */
#define REG_HMATRIXHS_SFR5 (0x4100A124) /**< \brief (HMATRIXHS) Special Function 5 */
#define REG_HMATRIXHS_SFR6 (0x4100A128) /**< \brief (HMATRIXHS) Special Function 6 */
#define REG_HMATRIXHS_SFR7 (0x4100A12C) /**< \brief (HMATRIXHS) Special Function 7 */
#define REG_HMATRIXHS_SFR8 (0x4100A130) /**< \brief (HMATRIXHS) Special Function 8 */
#define REG_HMATRIXHS_SFR9 (0x4100A134) /**< \brief (HMATRIXHS) Special Function 9 */
#define REG_HMATRIXHS_SFR10 (0x4100A138) /**< \brief (HMATRIXHS) Special Function 10 */
#define REG_HMATRIXHS_SFR11 (0x4100A13C) /**< \brief (HMATRIXHS) Special Function 11 */
#define REG_HMATRIXHS_SFR12 (0x4100A140) /**< \brief (HMATRIXHS) Special Function 12 */
#define REG_HMATRIXHS_SFR13 (0x4100A144) /**< \brief (HMATRIXHS) Special Function 13 */
#define REG_HMATRIXHS_SFR14 (0x4100A148) /**< \brief (HMATRIXHS) Special Function 14 */
#define REG_HMATRIXHS_SFR15 (0x4100A14C) /**< \brief (HMATRIXHS) Special Function 15 */
#else
#define REG_HMATRIXHS_MCFG0 (*(RwReg *)0x4100A000UL) /**< \brief (HMATRIXHS) Master Configuration 0 */
#define REG_HMATRIXHS_MCFG1 (*(RwReg *)0x4100A004UL) /**< \brief (HMATRIXHS) Master Configuration 1 */
#define REG_HMATRIXHS_MCFG2 (*(RwReg *)0x4100A008UL) /**< \brief (HMATRIXHS) Master Configuration 2 */
#define REG_HMATRIXHS_MCFG3 (*(RwReg *)0x4100A00CUL) /**< \brief (HMATRIXHS) Master Configuration 3 */
#define REG_HMATRIXHS_MCFG4 (*(RwReg *)0x4100A010UL) /**< \brief (HMATRIXHS) Master Configuration 4 */
#define REG_HMATRIXHS_MCFG5 (*(RwReg *)0x4100A014UL) /**< \brief (HMATRIXHS) Master Configuration 5 */
#define REG_HMATRIXHS_MCFG6 (*(RwReg *)0x4100A018UL) /**< \brief (HMATRIXHS) Master Configuration 6 */
#define REG_HMATRIXHS_MCFG7 (*(RwReg *)0x4100A01CUL) /**< \brief (HMATRIXHS) Master Configuration 7 */
#define REG_HMATRIXHS_MCFG8 (*(RwReg *)0x4100A020UL) /**< \brief (HMATRIXHS) Master Configuration 8 */
#define REG_HMATRIXHS_MCFG9 (*(RwReg *)0x4100A024UL) /**< \brief (HMATRIXHS) Master Configuration 9 */
#define REG_HMATRIXHS_MCFG10 (*(RwReg *)0x4100A028UL) /**< \brief (HMATRIXHS) Master Configuration 10 */
#define REG_HMATRIXHS_MCFG11 (*(RwReg *)0x4100A02CUL) /**< \brief (HMATRIXHS) Master Configuration 11 */
#define REG_HMATRIXHS_MCFG12 (*(RwReg *)0x4100A030UL) /**< \brief (HMATRIXHS) Master Configuration 12 */
#define REG_HMATRIXHS_MCFG13 (*(RwReg *)0x4100A034UL) /**< \brief (HMATRIXHS) Master Configuration 13 */
#define REG_HMATRIXHS_MCFG14 (*(RwReg *)0x4100A038UL) /**< \brief (HMATRIXHS) Master Configuration 14 */
#define REG_HMATRIXHS_MCFG15 (*(RwReg *)0x4100A03CUL) /**< \brief (HMATRIXHS) Master Configuration 15 */
#define REG_HMATRIXHS_SCFG0 (*(RwReg *)0x4100A040UL) /**< \brief (HMATRIXHS) Slave Configuration 0 */
#define REG_HMATRIXHS_SCFG1 (*(RwReg *)0x4100A044UL) /**< \brief (HMATRIXHS) Slave Configuration 1 */
#define REG_HMATRIXHS_SCFG2 (*(RwReg *)0x4100A048UL) /**< \brief (HMATRIXHS) Slave Configuration 2 */
#define REG_HMATRIXHS_SCFG3 (*(RwReg *)0x4100A04CUL) /**< \brief (HMATRIXHS) Slave Configuration 3 */
#define REG_HMATRIXHS_SCFG4 (*(RwReg *)0x4100A050UL) /**< \brief (HMATRIXHS) Slave Configuration 4 */
#define REG_HMATRIXHS_SCFG5 (*(RwReg *)0x4100A054UL) /**< \brief (HMATRIXHS) Slave Configuration 5 */
#define REG_HMATRIXHS_SCFG6 (*(RwReg *)0x4100A058UL) /**< \brief (HMATRIXHS) Slave Configuration 6 */
#define REG_HMATRIXHS_SCFG7 (*(RwReg *)0x4100A05CUL) /**< \brief (HMATRIXHS) Slave Configuration 7 */
#define REG_HMATRIXHS_SCFG8 (*(RwReg *)0x4100A060UL) /**< \brief (HMATRIXHS) Slave Configuration 8 */
#define REG_HMATRIXHS_SCFG9 (*(RwReg *)0x4100A064UL) /**< \brief (HMATRIXHS) Slave Configuration 9 */
#define REG_HMATRIXHS_SCFG10 (*(RwReg *)0x4100A068UL) /**< \brief (HMATRIXHS) Slave Configuration 10 */
#define REG_HMATRIXHS_SCFG11 (*(RwReg *)0x4100A06CUL) /**< \brief (HMATRIXHS) Slave Configuration 11 */
#define REG_HMATRIXHS_SCFG12 (*(RwReg *)0x4100A070UL) /**< \brief (HMATRIXHS) Slave Configuration 12 */
#define REG_HMATRIXHS_SCFG13 (*(RwReg *)0x4100A074UL) /**< \brief (HMATRIXHS) Slave Configuration 13 */
#define REG_HMATRIXHS_SCFG14 (*(RwReg *)0x4100A078UL) /**< \brief (HMATRIXHS) Slave Configuration 14 */
#define REG_HMATRIXHS_SCFG15 (*(RwReg *)0x4100A07CUL) /**< \brief (HMATRIXHS) Slave Configuration 15 */
#define REG_HMATRIXHS_PRAS0 (*(RwReg *)0x4100A080UL) /**< \brief (HMATRIXHS) Priority A for Slave 0 */
#define REG_HMATRIXHS_PRBS0 (*(RwReg *)0x4100A084UL) /**< \brief (HMATRIXHS) Priority B for Slave 0 */
#define REG_HMATRIXHS_PRAS1 (*(RwReg *)0x4100A088UL) /**< \brief (HMATRIXHS) Priority A for Slave 1 */
#define REG_HMATRIXHS_PRBS1 (*(RwReg *)0x4100A08CUL) /**< \brief (HMATRIXHS) Priority B for Slave 1 */
#define REG_HMATRIXHS_PRAS2 (*(RwReg *)0x4100A090UL) /**< \brief (HMATRIXHS) Priority A for Slave 2 */
#define REG_HMATRIXHS_PRBS2 (*(RwReg *)0x4100A094UL) /**< \brief (HMATRIXHS) Priority B for Slave 2 */
#define REG_HMATRIXHS_PRAS3 (*(RwReg *)0x4100A098UL) /**< \brief (HMATRIXHS) Priority A for Slave 3 */
#define REG_HMATRIXHS_PRBS3 (*(RwReg *)0x4100A09CUL) /**< \brief (HMATRIXHS) Priority B for Slave 3 */
#define REG_HMATRIXHS_MRCR (*(RwReg *)0x4100A100UL) /**< \brief (HMATRIXHS) Master Remap Control */
#define REG_HMATRIXHS_SFR0 (*(RwReg *)0x4100A110UL) /**< \brief (HMATRIXHS) Special Function 0 */
#define REG_HMATRIXHS_SFR1 (*(RwReg *)0x4100A114UL) /**< \brief (HMATRIXHS) Special Function 1 */
#define REG_HMATRIXHS_SFR2 (*(RwReg *)0x4100A118UL) /**< \brief (HMATRIXHS) Special Function 2 */
#define REG_HMATRIXHS_SFR3 (*(RwReg *)0x4100A11CUL) /**< \brief (HMATRIXHS) Special Function 3 */
#define REG_HMATRIXHS_SFR4 (*(RwReg *)0x4100A120UL) /**< \brief (HMATRIXHS) Special Function 4 */
#define REG_HMATRIXHS_SFR5 (*(RwReg *)0x4100A124UL) /**< \brief (HMATRIXHS) Special Function 5 */
#define REG_HMATRIXHS_SFR6 (*(RwReg *)0x4100A128UL) /**< \brief (HMATRIXHS) Special Function 6 */
#define REG_HMATRIXHS_SFR7 (*(RwReg *)0x4100A12CUL) /**< \brief (HMATRIXHS) Special Function 7 */
#define REG_HMATRIXHS_SFR8 (*(RwReg *)0x4100A130UL) /**< \brief (HMATRIXHS) Special Function 8 */
#define REG_HMATRIXHS_SFR9 (*(RwReg *)0x4100A134UL) /**< \brief (HMATRIXHS) Special Function 9 */
#define REG_HMATRIXHS_SFR10 (*(RwReg *)0x4100A138UL) /**< \brief (HMATRIXHS) Special Function 10 */
#define REG_HMATRIXHS_SFR11 (*(RwReg *)0x4100A13CUL) /**< \brief (HMATRIXHS) Special Function 11 */
#define REG_HMATRIXHS_SFR12 (*(RwReg *)0x4100A140UL) /**< \brief (HMATRIXHS) Special Function 12 */
#define REG_HMATRIXHS_SFR13 (*(RwReg *)0x4100A144UL) /**< \brief (HMATRIXHS) Special Function 13 */
#define REG_HMATRIXHS_SFR14 (*(RwReg *)0x4100A148UL) /**< \brief (HMATRIXHS) Special Function 14 */
#define REG_HMATRIXHS_SFR15 (*(RwReg *)0x4100A14CUL) /**< \brief (HMATRIXHS) Special Function 15 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for HMATRIXHS peripheral ========== */
#define HMATRIXHS_CLK_AHB_ID 4 // Index of AHB Clock in MCLK.AHBMASK register (MASK may be tied to 1 depending on chip integration)
#define HMATRIXHS_DEFINED
#endif /* _SAMC21_HMATRIXHS_INSTANCE_ */

60
lib/samc21/samc21/include/instance/mclk.h Normal file
View File

@@ -0,0 +1,60 @@
/**
* \file
*
* \brief Instance description for MCLK
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_MCLK_INSTANCE_
#define _SAMC21_MCLK_INSTANCE_
/* ========== Register definition for MCLK peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_MCLK_INTENCLR (0x40000801) /**< \brief (MCLK) Interrupt Enable Clear */
#define REG_MCLK_INTENSET (0x40000802) /**< \brief (MCLK) Interrupt Enable Set */
#define REG_MCLK_INTFLAG (0x40000803) /**< \brief (MCLK) Interrupt Flag Status and Clear */
#define REG_MCLK_CPUDIV (0x40000804) /**< \brief (MCLK) CPU Clock Division */
#define REG_MCLK_AHBMASK (0x40000810) /**< \brief (MCLK) AHB Mask */
#define REG_MCLK_APBAMASK (0x40000814) /**< \brief (MCLK) APBA Mask */
#define REG_MCLK_APBBMASK (0x40000818) /**< \brief (MCLK) APBB Mask */
#define REG_MCLK_APBCMASK (0x4000081C) /**< \brief (MCLK) APBC Mask */
#else
#define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000801UL) /**< \brief (MCLK) Interrupt Enable Clear */
#define REG_MCLK_INTENSET (*(RwReg8 *)0x40000802UL) /**< \brief (MCLK) Interrupt Enable Set */
#define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000803UL) /**< \brief (MCLK) Interrupt Flag Status and Clear */
#define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000804UL) /**< \brief (MCLK) CPU Clock Division */
#define REG_MCLK_AHBMASK (*(RwReg *)0x40000810UL) /**< \brief (MCLK) AHB Mask */
#define REG_MCLK_APBAMASK (*(RwReg *)0x40000814UL) /**< \brief (MCLK) APBA Mask */
#define REG_MCLK_APBBMASK (*(RwReg *)0x40000818UL) /**< \brief (MCLK) APBB Mask */
#define REG_MCLK_APBCMASK (*(RwReg *)0x4000081CUL) /**< \brief (MCLK) APBC Mask */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for MCLK peripheral ========== */
#define MCLK_CTRLA_MCSEL_GCLK 1
#define MCLK_CTRLA_MCSEL_OSC8M 0
#define MCLK_MCLK_CLK_APB_NUM 3
#define MCLK_SYSTEM_CLOCK 4000000 // System Clock Frequency at Reset
#endif /* _SAMC21_MCLK_INSTANCE_ */

89
lib/samc21/samc21/include/instance/mtb.h Normal file
View File

@@ -0,0 +1,89 @@
/**
* \file
*
* \brief Instance description for MTB
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_MTB_INSTANCE_
#define _SAMC21_MTB_INSTANCE_
/* ========== Register definition for MTB peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_MTB_POSITION (0x41008000) /**< \brief (MTB) MTB Position */
#define REG_MTB_MASTER (0x41008004) /**< \brief (MTB) MTB Master */
#define REG_MTB_FLOW (0x41008008) /**< \brief (MTB) MTB Flow */
#define REG_MTB_BASE (0x4100800C) /**< \brief (MTB) MTB Base */
#define REG_MTB_ITCTRL (0x41008F00) /**< \brief (MTB) MTB Integration Mode Control */
#define REG_MTB_CLAIMSET (0x41008FA0) /**< \brief (MTB) MTB Claim Set */
#define REG_MTB_CLAIMCLR (0x41008FA4) /**< \brief (MTB) MTB Claim Clear */
#define REG_MTB_LOCKACCESS (0x41008FB0) /**< \brief (MTB) MTB Lock Access */
#define REG_MTB_LOCKSTATUS (0x41008FB4) /**< \brief (MTB) MTB Lock Status */
#define REG_MTB_AUTHSTATUS (0x41008FB8) /**< \brief (MTB) MTB Authentication Status */
#define REG_MTB_DEVARCH (0x41008FBC) /**< \brief (MTB) MTB Device Architecture */
#define REG_MTB_DEVID (0x41008FC8) /**< \brief (MTB) MTB Device Configuration */
#define REG_MTB_DEVTYPE (0x41008FCC) /**< \brief (MTB) MTB Device Type */
#define REG_MTB_PID4 (0x41008FD0) /**< \brief (MTB) Peripheral Identification 4 */
#define REG_MTB_PID5 (0x41008FD4) /**< \brief (MTB) Peripheral Identification 5 */
#define REG_MTB_PID6 (0x41008FD8) /**< \brief (MTB) Peripheral Identification 6 */
#define REG_MTB_PID7 (0x41008FDC) /**< \brief (MTB) Peripheral Identification 7 */
#define REG_MTB_PID0 (0x41008FE0) /**< \brief (MTB) Peripheral Identification 0 */
#define REG_MTB_PID1 (0x41008FE4) /**< \brief (MTB) Peripheral Identification 1 */
#define REG_MTB_PID2 (0x41008FE8) /**< \brief (MTB) Peripheral Identification 2 */
#define REG_MTB_PID3 (0x41008FEC) /**< \brief (MTB) Peripheral Identification 3 */
#define REG_MTB_CID0 (0x41008FF0) /**< \brief (MTB) Component Identification 0 */
#define REG_MTB_CID1 (0x41008FF4) /**< \brief (MTB) Component Identification 1 */
#define REG_MTB_CID2 (0x41008FF8) /**< \brief (MTB) Component Identification 2 */
#define REG_MTB_CID3 (0x41008FFC) /**< \brief (MTB) Component Identification 3 */
#else
#define REG_MTB_POSITION (*(RwReg *)0x41008000UL) /**< \brief (MTB) MTB Position */
#define REG_MTB_MASTER (*(RwReg *)0x41008004UL) /**< \brief (MTB) MTB Master */
#define REG_MTB_FLOW (*(RwReg *)0x41008008UL) /**< \brief (MTB) MTB Flow */
#define REG_MTB_BASE (*(RoReg *)0x4100800CUL) /**< \brief (MTB) MTB Base */
#define REG_MTB_ITCTRL (*(RwReg *)0x41008F00UL) /**< \brief (MTB) MTB Integration Mode Control */
#define REG_MTB_CLAIMSET (*(RwReg *)0x41008FA0UL) /**< \brief (MTB) MTB Claim Set */
#define REG_MTB_CLAIMCLR (*(RwReg *)0x41008FA4UL) /**< \brief (MTB) MTB Claim Clear */
#define REG_MTB_LOCKACCESS (*(RwReg *)0x41008FB0UL) /**< \brief (MTB) MTB Lock Access */
#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41008FB4UL) /**< \brief (MTB) MTB Lock Status */
#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41008FB8UL) /**< \brief (MTB) MTB Authentication Status */
#define REG_MTB_DEVARCH (*(RoReg *)0x41008FBCUL) /**< \brief (MTB) MTB Device Architecture */
#define REG_MTB_DEVID (*(RoReg *)0x41008FC8UL) /**< \brief (MTB) MTB Device Configuration */
#define REG_MTB_DEVTYPE (*(RoReg *)0x41008FCCUL) /**< \brief (MTB) MTB Device Type */
#define REG_MTB_PID4 (*(RoReg *)0x41008FD0UL) /**< \brief (MTB) Peripheral Identification 4 */
#define REG_MTB_PID5 (*(RoReg *)0x41008FD4UL) /**< \brief (MTB) Peripheral Identification 5 */
#define REG_MTB_PID6 (*(RoReg *)0x41008FD8UL) /**< \brief (MTB) Peripheral Identification 6 */
#define REG_MTB_PID7 (*(RoReg *)0x41008FDCUL) /**< \brief (MTB) Peripheral Identification 7 */
#define REG_MTB_PID0 (*(RoReg *)0x41008FE0UL) /**< \brief (MTB) Peripheral Identification 0 */
#define REG_MTB_PID1 (*(RoReg *)0x41008FE4UL) /**< \brief (MTB) Peripheral Identification 1 */
#define REG_MTB_PID2 (*(RoReg *)0x41008FE8UL) /**< \brief (MTB) Peripheral Identification 2 */
#define REG_MTB_PID3 (*(RoReg *)0x41008FECUL) /**< \brief (MTB) Peripheral Identification 3 */
#define REG_MTB_CID0 (*(RoReg *)0x41008FF0UL) /**< \brief (MTB) Component Identification 0 */
#define REG_MTB_CID1 (*(RoReg *)0x41008FF4UL) /**< \brief (MTB) Component Identification 1 */
#define REG_MTB_CID2 (*(RoReg *)0x41008FF8UL) /**< \brief (MTB) Component Identification 2 */
#define REG_MTB_CID3 (*(RoReg *)0x41008FFCUL) /**< \brief (MTB) Component Identification 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMC21_MTB_INSTANCE_ */

85
lib/samc21/samc21/include/instance/nvmctrl.h Normal file
View File

@@ -0,0 +1,85 @@
/**
* \file
*
* \brief Instance description for NVMCTRL
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_NVMCTRL_INSTANCE_
#define _SAMC21_NVMCTRL_INSTANCE_
/* ========== Register definition for NVMCTRL peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */
#define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */
#define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */
#define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */
#define REG_NVMCTRL_INTENSET (0x41004010) /**< \brief (NVMCTRL) Interrupt Enable Set */
#define REG_NVMCTRL_INTFLAG (0x41004014) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
#define REG_NVMCTRL_STATUS (0x41004018) /**< \brief (NVMCTRL) Status */
#define REG_NVMCTRL_ADDR (0x4100401C) /**< \brief (NVMCTRL) Address */
#define REG_NVMCTRL_LOCK (0x41004020) /**< \brief (NVMCTRL) Lock Section */
#define REG_NVMCTRL_PBLDATA0 (0x41004028) /**< \brief (NVMCTRL) Page Buffer Load Data 0 */
#define REG_NVMCTRL_PBLDATA1 (0x4100402C) /**< \brief (NVMCTRL) Page Buffer Load Data 1 */
#else
#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */
#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004UL) /**< \brief (NVMCTRL) Control B */
#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */
#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */
#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Enable Set */
#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018UL) /**< \brief (NVMCTRL) Status */
#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CUL) /**< \brief (NVMCTRL) Address */
#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020UL) /**< \brief (NVMCTRL) Lock Section */
#define REG_NVMCTRL_PBLDATA0 (*(RoReg *)0x41004028UL) /**< \brief (NVMCTRL) Page Buffer Load Data 0 */
#define REG_NVMCTRL_PBLDATA1 (*(RoReg *)0x4100402CUL) /**< \brief (NVMCTRL) Page Buffer Load Data 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for NVMCTRL peripheral ========== */
#define NVMCTRL_AUX0_ADDRESS 0x00804000
#define NVMCTRL_AUX1_ADDRESS 0x00806000
#define NVMCTRL_AUX2_ADDRESS 0x00808000
#define NVMCTRL_AUX3_ADDRESS 0x0080A000
#define NVMCTRL_CLK_AHB_DOMAIN // Clock domain of AHB clock
#define NVMCTRL_CLK_AHB_ID 5 // Index of AHB Clock in PM.AHBMASK register
#define NVMCTRL_CLK_AHB_ID_PICACHU 11 // Index of PICACHU AHB Clock
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF
#define NVMCTRL_FLASH_SIZE 262144
#define NVMCTRL_GCLK_ID 39 // Index of Generic Clock for test
#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
#define NVMCTRL_PAGE_HW 32
#define NVMCTRL_PAGE_SIZE 64
#define NVMCTRL_PAGE_W 16
#define NVMCTRL_PMSB 3
#define NVMCTRL_PSZ_BITS 6
#define NVMCTRL_ROW_PAGES 4
#define NVMCTRL_ROW_SIZE 256
#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF
#define NVMCTRL_RWWEE_PAGES 128
#define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area
#endif /* _SAMC21_NVMCTRL_INSTANCE_ */

61
lib/samc21/samc21/include/instance/osc32kctrl.h Normal file
View File

@@ -0,0 +1,61 @@
/**
* \file
*
* \brief Instance description for OSC32KCTRL
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_OSC32KCTRL_INSTANCE_
#define _SAMC21_OSC32KCTRL_INSTANCE_
/* ========== Register definition for OSC32KCTRL peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_OSC32KCTRL_INTENCLR (0x40001400) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
#define REG_OSC32KCTRL_INTENSET (0x40001404) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
#define REG_OSC32KCTRL_INTFLAG (0x40001408) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
#define REG_OSC32KCTRL_STATUS (0x4000140C) /**< \brief (OSC32KCTRL) Power and Clocks Status */
#define REG_OSC32KCTRL_RTCCTRL (0x40001410) /**< \brief (OSC32KCTRL) Clock selection */
#define REG_OSC32KCTRL_XOSC32K (0x40001414) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
#define REG_OSC32KCTRL_CFDCTRL (0x40001416) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
#define REG_OSC32KCTRL_EVCTRL (0x40001417) /**< \brief (OSC32KCTRL) Event Control */
#define REG_OSC32KCTRL_OSC32K (0x40001418) /**< \brief (OSC32KCTRL) 32kHz Internal Oscillator (OSC32K) Control */
#define REG_OSC32KCTRL_OSCULP32K (0x4000141C) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
#else
#define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001400UL) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
#define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001404UL) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
#define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001408UL) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
#define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000140CUL) /**< \brief (OSC32KCTRL) Power and Clocks Status */
#define REG_OSC32KCTRL_RTCCTRL (*(RwReg *)0x40001410UL) /**< \brief (OSC32KCTRL) Clock selection */
#define REG_OSC32KCTRL_XOSC32K (*(RwReg16*)0x40001414UL) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
#define REG_OSC32KCTRL_CFDCTRL (*(RwReg8 *)0x40001416UL) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
#define REG_OSC32KCTRL_EVCTRL (*(RwReg8 *)0x40001417UL) /**< \brief (OSC32KCTRL) Event Control */
#define REG_OSC32KCTRL_OSC32K (*(RwReg *)0x40001418UL) /**< \brief (OSC32KCTRL) 32kHz Internal Oscillator (OSC32K) Control */
#define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000141CUL) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for OSC32KCTRL peripheral ========== */
#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6
#endif /* _SAMC21_OSC32KCTRL_INSTANCE_ */

81
lib/samc21/samc21/include/instance/oscctrl.h Normal file
View File

@@ -0,0 +1,81 @@
/**
* \file
*
* \brief Instance description for OSCCTRL
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_OSCCTRL_INSTANCE_
#define _SAMC21_OSCCTRL_INSTANCE_
/* ========== Register definition for OSCCTRL peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_OSCCTRL_INTENCLR (0x40001000) /**< \brief (OSCCTRL) Interrupt Enable Clear */
#define REG_OSCCTRL_INTENSET (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Set */
#define REG_OSCCTRL_INTFLAG (0x40001008) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
#define REG_OSCCTRL_STATUS (0x4000100C) /**< \brief (OSCCTRL) Power and Clocks Status */
#define REG_OSCCTRL_XOSCCTRL (0x40001010) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
#define REG_OSCCTRL_CFDPRESC (0x40001012) /**< \brief (OSCCTRL) Clock Failure Detector Prescaler */
#define REG_OSCCTRL_EVCTRL (0x40001013) /**< \brief (OSCCTRL) Event Control */
#define REG_OSCCTRL_OSC48MCTRL (0x40001014) /**< \brief (OSCCTRL) 48MHz Internal Oscillator (OSC48M) Control */
#define REG_OSCCTRL_OSC48MDIV (0x40001015) /**< \brief (OSCCTRL) OSC48M Divider */
#define REG_OSCCTRL_OSC48MSTUP (0x40001016) /**< \brief (OSCCTRL) OSC48M Startup Time */
#define REG_OSCCTRL_OSC48MSYNCBUSY (0x40001018) /**< \brief (OSCCTRL) OSC48M Synchronization Busy */
#define REG_OSCCTRL_DPLLCTRLA (0x4000101C) /**< \brief (OSCCTRL) DPLL Control */
#define REG_OSCCTRL_DPLLRATIO (0x40001020) /**< \brief (OSCCTRL) DPLL Ratio Control */
#define REG_OSCCTRL_DPLLCTRLB (0x40001024) /**< \brief (OSCCTRL) Digital Core Configuration */
#define REG_OSCCTRL_DPLLPRESC (0x40001028) /**< \brief (OSCCTRL) DPLL Prescaler */
#define REG_OSCCTRL_DPLLSYNCBUSY (0x4000102C) /**< \brief (OSCCTRL) DPLL Synchronization Busy */
#define REG_OSCCTRL_DPLLSTATUS (0x40001030) /**< \brief (OSCCTRL) DPLL Status */
#define REG_OSCCTRL_CAL48M (0x40001038) /**< \brief (OSCCTRL) 48MHz Oscillator Calibration */
#else
#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001000UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */
#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Set */
#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
#define REG_OSCCTRL_STATUS (*(RoReg *)0x4000100CUL) /**< \brief (OSCCTRL) Power and Clocks Status */
#define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40001010UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
#define REG_OSCCTRL_CFDPRESC (*(RwReg8 *)0x40001012UL) /**< \brief (OSCCTRL) Clock Failure Detector Prescaler */
#define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001013UL) /**< \brief (OSCCTRL) Event Control */
#define REG_OSCCTRL_OSC48MCTRL (*(RwReg8 *)0x40001014UL) /**< \brief (OSCCTRL) 48MHz Internal Oscillator (OSC48M) Control */
#define REG_OSCCTRL_OSC48MDIV (*(RwReg8 *)0x40001015UL) /**< \brief (OSCCTRL) OSC48M Divider */
#define REG_OSCCTRL_OSC48MSTUP (*(RwReg8 *)0x40001016UL) /**< \brief (OSCCTRL) OSC48M Startup Time */
#define REG_OSCCTRL_OSC48MSYNCBUSY (*(RoReg *)0x40001018UL) /**< \brief (OSCCTRL) OSC48M Synchronization Busy */
#define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x4000101CUL) /**< \brief (OSCCTRL) DPLL Control */
#define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x40001020UL) /**< \brief (OSCCTRL) DPLL Ratio Control */
#define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40001024UL) /**< \brief (OSCCTRL) Digital Core Configuration */
#define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40001028UL) /**< \brief (OSCCTRL) DPLL Prescaler */
#define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x4000102CUL) /**< \brief (OSCCTRL) DPLL Synchronization Busy */
#define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x40001030UL) /**< \brief (OSCCTRL) DPLL Status */
#define REG_OSCCTRL_CAL48M (*(RwReg *)0x40001038UL) /**< \brief (OSCCTRL) 48MHz Oscillator Calibration */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for OSCCTRL peripheral ========== */
#define OSCCTRL_GCLK_ID_FDPLL 0 // Index of Generic Clock for DPLL
#define OSCCTRL_GCLK_ID_FDPLL32K 1 // Index of Generic Clock for DPLL 32K
#define OSCCTRL_FDPLL_VERSION 0x211
#define OSCCTRL_OSC48M_VERSION 0x101
#define OSCCTRL_XOSC_VERSION 0x201
#endif /* _SAMC21_OSCCTRL_INSTANCE_ */

66
lib/samc21/samc21/include/instance/pac.h Normal file
View File

@@ -0,0 +1,66 @@
/**
* \file
*
* \brief Instance description for PAC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_PAC_INSTANCE_
#define _SAMC21_PAC_INSTANCE_
/* ========== Register definition for PAC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PAC_WRCTRL (0x40000000) /**< \brief (PAC) Write control */
#define REG_PAC_EVCTRL (0x40000004) /**< \brief (PAC) Event control */
#define REG_PAC_INTENCLR (0x40000008) /**< \brief (PAC) Interrupt enable clear */
#define REG_PAC_INTENSET (0x40000009) /**< \brief (PAC) Interrupt enable set */
#define REG_PAC_INTFLAGAHB (0x40000010) /**< \brief (PAC) Bridge interrupt flag status */
#define REG_PAC_INTFLAGA (0x40000014) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
#define REG_PAC_INTFLAGB (0x40000018) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
#define REG_PAC_INTFLAGC (0x4000001C) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
#define REG_PAC_STATUSA (0x40000034) /**< \brief (PAC) Peripheral write protection status - Bridge A */
#define REG_PAC_STATUSB (0x40000038) /**< \brief (PAC) Peripheral write protection status - Bridge B */
#define REG_PAC_STATUSC (0x4000003C) /**< \brief (PAC) Peripheral write protection status - Bridge C */
#else
#define REG_PAC_WRCTRL (*(RwReg *)0x40000000UL) /**< \brief (PAC) Write control */
#define REG_PAC_EVCTRL (*(RwReg8 *)0x40000004UL) /**< \brief (PAC) Event control */
#define REG_PAC_INTENCLR (*(RwReg8 *)0x40000008UL) /**< \brief (PAC) Interrupt enable clear */
#define REG_PAC_INTENSET (*(RwReg8 *)0x40000009UL) /**< \brief (PAC) Interrupt enable set */
#define REG_PAC_INTFLAGAHB (*(RwReg *)0x40000010UL) /**< \brief (PAC) Bridge interrupt flag status */
#define REG_PAC_INTFLAGA (*(RwReg *)0x40000014UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
#define REG_PAC_INTFLAGB (*(RwReg *)0x40000018UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
#define REG_PAC_INTFLAGC (*(RwReg *)0x4000001CUL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
#define REG_PAC_STATUSA (*(RoReg *)0x40000034UL) /**< \brief (PAC) Peripheral write protection status - Bridge A */
#define REG_PAC_STATUSB (*(RoReg *)0x40000038UL) /**< \brief (PAC) Peripheral write protection status - Bridge B */
#define REG_PAC_STATUSC (*(RoReg *)0x4000003CUL) /**< \brief (PAC) Peripheral write protection status - Bridge C */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PAC peripheral ========== */
#define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock
#define PAC_CLK_AHB_ID 10 // AHB clock index
#define PAC_HPB_NUM 3 // Number of bridges AHB/APB
#define PAC_INTFLAG_NUM 4 // Number of intflag registers
#endif /* _SAMC21_PAC_INSTANCE_ */

46
lib/samc21/samc21/include/instance/pm.h Normal file
View File

@@ -0,0 +1,46 @@
/**
* \file
*
* \brief Instance description for PM
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_PM_INSTANCE_
#define _SAMC21_PM_INSTANCE_
/* ========== Register definition for PM peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PM_SLEEPCFG (0x40000401) /**< \brief (PM) Sleep Configuration */
#define REG_PM_STDBYCFG (0x40000408) /**< \brief (PM) Standby Configuration */
#else
#define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Configuration */
#define REG_PM_STDBYCFG (*(RwReg16*)0x40000408UL) /**< \brief (PM) Standby Configuration */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PM peripheral ========== */
#define PM_BIAS_RAM_HS 1 // one if RAM HS can be back biased
#define PM_PD_NUM 0 // Number of switchable Power Domain
#endif /* _SAMC21_PM_INSTANCE_ */

127
lib/samc21/samc21/include/instance/port.h Normal file
View File

@@ -0,0 +1,127 @@
/**
* \file
*
* \brief Instance description for PORT
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_PORT_INSTANCE_
#define _SAMC21_PORT_INSTANCE_
/* ========== Register definition for PORT peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PORT_DIR0 (0x41000000) /**< \brief (PORT) Data Direction 0 */
#define REG_PORT_DIRCLR0 (0x41000004) /**< \brief (PORT) Data Direction Clear 0 */
#define REG_PORT_DIRSET0 (0x41000008) /**< \brief (PORT) Data Direction Set 0 */
#define REG_PORT_DIRTGL0 (0x4100000C) /**< \brief (PORT) Data Direction Toggle 0 */
#define REG_PORT_OUT0 (0x41000010) /**< \brief (PORT) Data Output Value 0 */
#define REG_PORT_OUTCLR0 (0x41000014) /**< \brief (PORT) Data Output Value Clear 0 */
#define REG_PORT_OUTSET0 (0x41000018) /**< \brief (PORT) Data Output Value Set 0 */
#define REG_PORT_OUTTGL0 (0x4100001C) /**< \brief (PORT) Data Output Value Toggle 0 */
#define REG_PORT_IN0 (0x41000020) /**< \brief (PORT) Data Input Value 0 */
#define REG_PORT_CTRL0 (0x41000024) /**< \brief (PORT) Control 0 */
#define REG_PORT_WRCONFIG0 (0x41000028) /**< \brief (PORT) Write Configuration 0 */
#define REG_PORT_EVCTRL0 (0x4100002C) /**< \brief (PORT) Event Input Control 0 */
#define REG_PORT_PMUX0 (0x41000030) /**< \brief (PORT) Peripheral Multiplexing 0 */
#define REG_PORT_PINCFG0 (0x41000040) /**< \brief (PORT) Pin Configuration 0 */
#define REG_PORT_DIR1 (0x41000080) /**< \brief (PORT) Data Direction 1 */
#define REG_PORT_DIRCLR1 (0x41000084) /**< \brief (PORT) Data Direction Clear 1 */
#define REG_PORT_DIRSET1 (0x41000088) /**< \brief (PORT) Data Direction Set 1 */
#define REG_PORT_DIRTGL1 (0x4100008C) /**< \brief (PORT) Data Direction Toggle 1 */
#define REG_PORT_OUT1 (0x41000090) /**< \brief (PORT) Data Output Value 1 */
#define REG_PORT_OUTCLR1 (0x41000094) /**< \brief (PORT) Data Output Value Clear 1 */
#define REG_PORT_OUTSET1 (0x41000098) /**< \brief (PORT) Data Output Value Set 1 */
#define REG_PORT_OUTTGL1 (0x4100009C) /**< \brief (PORT) Data Output Value Toggle 1 */
#define REG_PORT_IN1 (0x410000A0) /**< \brief (PORT) Data Input Value 1 */
#define REG_PORT_CTRL1 (0x410000A4) /**< \brief (PORT) Control 1 */
#define REG_PORT_WRCONFIG1 (0x410000A8) /**< \brief (PORT) Write Configuration 1 */
#define REG_PORT_EVCTRL1 (0x410000AC) /**< \brief (PORT) Event Input Control 1 */
#define REG_PORT_PMUX1 (0x410000B0) /**< \brief (PORT) Peripheral Multiplexing 1 */
#define REG_PORT_PINCFG1 (0x410000C0) /**< \brief (PORT) Pin Configuration 1 */
#else
#define REG_PORT_DIR0 (*(RwReg *)0x41000000UL) /**< \brief (PORT) Data Direction 0 */
#define REG_PORT_DIRCLR0 (*(RwReg *)0x41000004UL) /**< \brief (PORT) Data Direction Clear 0 */
#define REG_PORT_DIRSET0 (*(RwReg *)0x41000008UL) /**< \brief (PORT) Data Direction Set 0 */
#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100000CUL) /**< \brief (PORT) Data Direction Toggle 0 */
#define REG_PORT_OUT0 (*(RwReg *)0x41000010UL) /**< \brief (PORT) Data Output Value 0 */
#define REG_PORT_OUTCLR0 (*(RwReg *)0x41000014UL) /**< \brief (PORT) Data Output Value Clear 0 */
#define REG_PORT_OUTSET0 (*(RwReg *)0x41000018UL) /**< \brief (PORT) Data Output Value Set 0 */
#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100001CUL) /**< \brief (PORT) Data Output Value Toggle 0 */
#define REG_PORT_IN0 (*(RoReg *)0x41000020UL) /**< \brief (PORT) Data Input Value 0 */
#define REG_PORT_CTRL0 (*(RwReg *)0x41000024UL) /**< \brief (PORT) Control 0 */
#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41000028UL) /**< \brief (PORT) Write Configuration 0 */
#define REG_PORT_EVCTRL0 (*(RwReg *)0x4100002CUL) /**< \brief (PORT) Event Input Control 0 */
#define REG_PORT_PMUX0 (*(RwReg8 *)0x41000030UL) /**< \brief (PORT) Peripheral Multiplexing 0 */
#define REG_PORT_PINCFG0 (*(RwReg8 *)0x41000040UL) /**< \brief (PORT) Pin Configuration 0 */
#define REG_PORT_DIR1 (*(RwReg *)0x41000080UL) /**< \brief (PORT) Data Direction 1 */
#define REG_PORT_DIRCLR1 (*(RwReg *)0x41000084UL) /**< \brief (PORT) Data Direction Clear 1 */
#define REG_PORT_DIRSET1 (*(RwReg *)0x41000088UL) /**< \brief (PORT) Data Direction Set 1 */
#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100008CUL) /**< \brief (PORT) Data Direction Toggle 1 */
#define REG_PORT_OUT1 (*(RwReg *)0x41000090UL) /**< \brief (PORT) Data Output Value 1 */
#define REG_PORT_OUTCLR1 (*(RwReg *)0x41000094UL) /**< \brief (PORT) Data Output Value Clear 1 */
#define REG_PORT_OUTSET1 (*(RwReg *)0x41000098UL) /**< \brief (PORT) Data Output Value Set 1 */
#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100009CUL) /**< \brief (PORT) Data Output Value Toggle 1 */
#define REG_PORT_IN1 (*(RoReg *)0x410000A0UL) /**< \brief (PORT) Data Input Value 1 */
#define REG_PORT_CTRL1 (*(RwReg *)0x410000A4UL) /**< \brief (PORT) Control 1 */
#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410000A8UL) /**< \brief (PORT) Write Configuration 1 */
#define REG_PORT_EVCTRL1 (*(RwReg *)0x410000ACUL) /**< \brief (PORT) Event Input Control 1 */
#define REG_PORT_PMUX1 (*(RwReg8 *)0x410000B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */
#define REG_PORT_PINCFG1 (*(RwReg8 *)0x410000C0UL) /**< \brief (PORT) Pin Configuration 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PORT peripheral ========== */
#define PORT_BITS 64
#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_DRVSTR 1 // DRVSTR supported
#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_DRVSTR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC0C3FFFF }
#define PORT_EV_NUM 4
#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_ODRAIN 0 // ODRAIN supported
#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000 }
#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000 }
#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F }
#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000 }
#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F }
#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_PMUXBIT3_IMPLEMENTED { 0xC3CF0FF0, 0x00C3CFC7 }
#define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000 }
#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_SLEWLIM 0 // SLEWLIM supported
#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000 }
#endif /* _SAMC21_PORT_INSTANCE_ */

41
lib/samc21/samc21/include/instance/ptc.h Normal file
View File

@@ -0,0 +1,41 @@
/**
* \file
*
* \brief Instance description for PTC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_PTC_INSTANCE_
#define _SAMC21_PTC_INSTANCE_
/* ========== Instance parameters for PTC peripheral ========== */
#define PTC_DMAC_ID_EOC 46 // Index of DMA EOC trigger
#define PTC_DMAC_ID_SEQ 48 // Index of DMA SEQ trigger
#define PTC_DMAC_ID_WCOMP 47 // Index of DMA WCOMP trigger
#define PTC_GCLK_ID 37 // Index of Generic Clock
#define PTC_X_LINES_NUM 16 // Number of X lines
#define PTC_Y_LINES_NUM 32 // Number of Y lines
#endif /* _SAMC21_PTC_INSTANCE_ */

43
lib/samc21/samc21/include/instance/rstc.h Normal file
View File

@@ -0,0 +1,43 @@
/**
* \file
*
* \brief Instance description for RSTC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_RSTC_INSTANCE_
#define _SAMC21_RSTC_INSTANCE_
/* ========== Register definition for RSTC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RSTC_RCAUSE (0x40000C00) /**< \brief (RSTC) Reset Cause */
#else
#define REG_RSTC_RCAUSE (*(RoReg8 *)0x40000C00UL) /**< \brief (RSTC) Reset Cause */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for RSTC peripheral ========== */
#define RSTC_NUMBER_OF_EXTWAKE 0 // number of external wakeup line
#endif /* _SAMC21_RSTC_INSTANCE_ */

103
lib/samc21/samc21/include/instance/rtc.h Normal file
View File

@@ -0,0 +1,103 @@
/**
* \file
*
* \brief Instance description for RTC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_RTC_INSTANCE_
#define _SAMC21_RTC_INSTANCE_
/* ========== Register definition for RTC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RTC_DBGCTRL (0x4000240E) /**< \brief (RTC) Debug Control */
#define REG_RTC_FREQCORR (0x40002414) /**< \brief (RTC) Frequency Correction */
#define REG_RTC_MODE0_CTRLA (0x40002400) /**< \brief (RTC) MODE0 Control A */
#define REG_RTC_MODE0_EVCTRL (0x40002404) /**< \brief (RTC) MODE0 Event Control */
#define REG_RTC_MODE0_INTENCLR (0x40002408) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
#define REG_RTC_MODE0_INTENSET (0x4000240A) /**< \brief (RTC) MODE0 Interrupt Enable Set */
#define REG_RTC_MODE0_INTFLAG (0x4000240C) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
#define REG_RTC_MODE0_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE0 Synchronization Busy Status */
#define REG_RTC_MODE0_COUNT (0x40002418) /**< \brief (RTC) MODE0 Counter Value */
#define REG_RTC_MODE0_COMP0 (0x40002420) /**< \brief (RTC) MODE0 Compare 0 Value */
#define REG_RTC_MODE1_CTRLA (0x40002400) /**< \brief (RTC) MODE1 Control A */
#define REG_RTC_MODE1_EVCTRL (0x40002404) /**< \brief (RTC) MODE1 Event Control */
#define REG_RTC_MODE1_INTENCLR (0x40002408) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
#define REG_RTC_MODE1_INTENSET (0x4000240A) /**< \brief (RTC) MODE1 Interrupt Enable Set */
#define REG_RTC_MODE1_INTFLAG (0x4000240C) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
#define REG_RTC_MODE1_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE1 Synchronization Busy Status */
#define REG_RTC_MODE1_COUNT (0x40002418) /**< \brief (RTC) MODE1 Counter Value */
#define REG_RTC_MODE1_PER (0x4000241C) /**< \brief (RTC) MODE1 Counter Period */
#define REG_RTC_MODE1_COMP0 (0x40002420) /**< \brief (RTC) MODE1 Compare 0 Value */
#define REG_RTC_MODE1_COMP1 (0x40002422) /**< \brief (RTC) MODE1 Compare 1 Value */
#define REG_RTC_MODE2_CTRLA (0x40002400) /**< \brief (RTC) MODE2 Control A */
#define REG_RTC_MODE2_EVCTRL (0x40002404) /**< \brief (RTC) MODE2 Event Control */
#define REG_RTC_MODE2_INTENCLR (0x40002408) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
#define REG_RTC_MODE2_INTENSET (0x4000240A) /**< \brief (RTC) MODE2 Interrupt Enable Set */
#define REG_RTC_MODE2_INTFLAG (0x4000240C) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
#define REG_RTC_MODE2_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE2 Synchronization Busy Status */
#define REG_RTC_MODE2_CLOCK (0x40002418) /**< \brief (RTC) MODE2 Clock Value */
#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
#define REG_RTC_MODE2_ALARM_MASK0 (0x40002424) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
#else
#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000240EUL) /**< \brief (RTC) Debug Control */
#define REG_RTC_FREQCORR (*(RwReg8 *)0x40002414UL) /**< \brief (RTC) Frequency Correction */
#define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */
#define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE0 Event Control */
#define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
#define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enable Set */
#define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
#define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE0 Synchronization Busy Status */
#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE0 Counter Value */
#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE0 Compare 0 Value */
#define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */
#define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE1 Event Control */
#define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
#define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enable Set */
#define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
#define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE1 Synchronization Busy Status */
#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418UL) /**< \brief (RTC) MODE1 Counter Value */
#define REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CUL) /**< \brief (RTC) MODE1 Counter Period */
#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002420UL) /**< \brief (RTC) MODE1 Compare 0 Value */
#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002422UL) /**< \brief (RTC) MODE1 Compare 1 Value */
#define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE2 Control A */
#define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE2 Event Control */
#define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
#define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE2 Interrupt Enable Set */
#define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
#define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE2 Synchronization Busy Status */
#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE2 Clock Value */
#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg8 *)0x40002424UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for RTC peripheral ========== */
#define RTC_ALARM_NUM 1 // Number of Alarms
#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators
#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators
#define RTC_GPR_NUM 0 // Number of General-Purpose Registers
#define RTC_PER_NUM 8 // Number of Periodic Intervals
#endif /* _SAMC21_RTC_INSTANCE_ */

87
lib/samc21/samc21/include/instance/sdadc.h Normal file
View File

@@ -0,0 +1,87 @@
/**
* \file
*
* \brief Instance description for SDADC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SDADC_INSTANCE_
#define _SAMC21_SDADC_INSTANCE_
/* ========== Register definition for SDADC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SDADC_CTRLA (0x42004C00) /**< \brief (SDADC) Control A */
#define REG_SDADC_REFCTRL (0x42004C01) /**< \brief (SDADC) Reference Control */
#define REG_SDADC_CTRLB (0x42004C02) /**< \brief (SDADC) Control B */
#define REG_SDADC_EVCTRL (0x42004C04) /**< \brief (SDADC) Event Control */
#define REG_SDADC_INTENCLR (0x42004C05) /**< \brief (SDADC) Interrupt Enable Clear */
#define REG_SDADC_INTENSET (0x42004C06) /**< \brief (SDADC) Interrupt Enable Set */
#define REG_SDADC_INTFLAG (0x42004C07) /**< \brief (SDADC) Interrupt Flag Status and Clear */
#define REG_SDADC_SEQSTATUS (0x42004C08) /**< \brief (SDADC) Sequence Status */
#define REG_SDADC_INPUTCTRL (0x42004C09) /**< \brief (SDADC) Input Control */
#define REG_SDADC_CTRLC (0x42004C0A) /**< \brief (SDADC) Control C */
#define REG_SDADC_WINCTRL (0x42004C0B) /**< \brief (SDADC) Window Monitor Control */
#define REG_SDADC_WINLT (0x42004C0C) /**< \brief (SDADC) Window Monitor Lower Threshold */
#define REG_SDADC_WINUT (0x42004C10) /**< \brief (SDADC) Window Monitor Upper Threshold */
#define REG_SDADC_OFFSETCORR (0x42004C14) /**< \brief (SDADC) Offset Correction */
#define REG_SDADC_GAINCORR (0x42004C18) /**< \brief (SDADC) Gain Correction */
#define REG_SDADC_SHIFTCORR (0x42004C1A) /**< \brief (SDADC) Shift Correction */
#define REG_SDADC_SWTRIG (0x42004C1C) /**< \brief (SDADC) Software Trigger */
#define REG_SDADC_SYNCBUSY (0x42004C20) /**< \brief (SDADC) Synchronization Busy */
#define REG_SDADC_RESULT (0x42004C24) /**< \brief (SDADC) Result */
#define REG_SDADC_SEQCTRL (0x42004C28) /**< \brief (SDADC) Sequence Control */
#define REG_SDADC_ANACTRL (0x42004C2C) /**< \brief (SDADC) Analog Control */
#define REG_SDADC_DBGCTRL (0x42004C2E) /**< \brief (SDADC) Debug Control */
#else
#define REG_SDADC_CTRLA (*(RwReg8 *)0x42004C00UL) /**< \brief (SDADC) Control A */
#define REG_SDADC_REFCTRL (*(RwReg8 *)0x42004C01UL) /**< \brief (SDADC) Reference Control */
#define REG_SDADC_CTRLB (*(RwReg16*)0x42004C02UL) /**< \brief (SDADC) Control B */
#define REG_SDADC_EVCTRL (*(RwReg8 *)0x42004C04UL) /**< \brief (SDADC) Event Control */
#define REG_SDADC_INTENCLR (*(RwReg8 *)0x42004C05UL) /**< \brief (SDADC) Interrupt Enable Clear */
#define REG_SDADC_INTENSET (*(RwReg8 *)0x42004C06UL) /**< \brief (SDADC) Interrupt Enable Set */
#define REG_SDADC_INTFLAG (*(RwReg8 *)0x42004C07UL) /**< \brief (SDADC) Interrupt Flag Status and Clear */
#define REG_SDADC_SEQSTATUS (*(RoReg8 *)0x42004C08UL) /**< \brief (SDADC) Sequence Status */
#define REG_SDADC_INPUTCTRL (*(RwReg8 *)0x42004C09UL) /**< \brief (SDADC) Input Control */
#define REG_SDADC_CTRLC (*(RwReg8 *)0x42004C0AUL) /**< \brief (SDADC) Control C */
#define REG_SDADC_WINCTRL (*(RwReg8 *)0x42004C0BUL) /**< \brief (SDADC) Window Monitor Control */
#define REG_SDADC_WINLT (*(RwReg *)0x42004C0CUL) /**< \brief (SDADC) Window Monitor Lower Threshold */
#define REG_SDADC_WINUT (*(RwReg *)0x42004C10UL) /**< \brief (SDADC) Window Monitor Upper Threshold */
#define REG_SDADC_OFFSETCORR (*(RwReg *)0x42004C14UL) /**< \brief (SDADC) Offset Correction */
#define REG_SDADC_GAINCORR (*(RwReg16*)0x42004C18UL) /**< \brief (SDADC) Gain Correction */
#define REG_SDADC_SHIFTCORR (*(RwReg8 *)0x42004C1AUL) /**< \brief (SDADC) Shift Correction */
#define REG_SDADC_SWTRIG (*(RwReg8 *)0x42004C1CUL) /**< \brief (SDADC) Software Trigger */
#define REG_SDADC_SYNCBUSY (*(RoReg *)0x42004C20UL) /**< \brief (SDADC) Synchronization Busy */
#define REG_SDADC_RESULT (*(RoReg *)0x42004C24UL) /**< \brief (SDADC) Result */
#define REG_SDADC_SEQCTRL (*(RwReg8 *)0x42004C28UL) /**< \brief (SDADC) Sequence Control */
#define REG_SDADC_ANACTRL (*(RwReg8 *)0x42004C2CUL) /**< \brief (SDADC) Analog Control */
#define REG_SDADC_DBGCTRL (*(RwReg8 *)0x42004C2EUL) /**< \brief (SDADC) Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SDADC peripheral ========== */
#define SDADC_DMAC_ID_RESRDY 44 // Index of DMA RESRDY trigger
#define SDADC_EXT_CHANNELS 3 // Number of external channels
#define SDADC_GCLK_ID 35 // Index of generic clock
#endif /* _SAMC21_SDADC_INSTANCE_ */

132
lib/samc21/samc21/include/instance/sercom0.h Normal file
View File

@@ -0,0 +1,132 @@
/**
* \file
*
* \brief Instance description for SERCOM0
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SERCOM0_INSTANCE_
#define _SAMC21_SERCOM0_INSTANCE_
/* ========== Register definition for SERCOM0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM0_I2CM_CTRLA (0x42000400) /**< \brief (SERCOM0) I2CM Control A */
#define REG_SERCOM0_I2CM_CTRLB (0x42000404) /**< \brief (SERCOM0) I2CM Control B */
#define REG_SERCOM0_I2CM_BAUD (0x4200040C) /**< \brief (SERCOM0) I2CM Baud Rate */
#define REG_SERCOM0_I2CM_INTENCLR (0x42000414) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
#define REG_SERCOM0_I2CM_INTENSET (0x42000416) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
#define REG_SERCOM0_I2CM_INTFLAG (0x42000418) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CM_STATUS (0x4200041A) /**< \brief (SERCOM0) I2CM Status */
#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) I2CM Synchronization Busy */
#define REG_SERCOM0_I2CM_ADDR (0x42000424) /**< \brief (SERCOM0) I2CM Address */
#define REG_SERCOM0_I2CM_DATA (0x42000428) /**< \brief (SERCOM0) I2CM Data */
#define REG_SERCOM0_I2CM_DBGCTRL (0x42000430) /**< \brief (SERCOM0) I2CM Debug Control */
#define REG_SERCOM0_I2CS_CTRLA (0x42000400) /**< \brief (SERCOM0) I2CS Control A */
#define REG_SERCOM0_I2CS_CTRLB (0x42000404) /**< \brief (SERCOM0) I2CS Control B */
#define REG_SERCOM0_I2CS_INTENCLR (0x42000414) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
#define REG_SERCOM0_I2CS_INTENSET (0x42000416) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
#define REG_SERCOM0_I2CS_INTFLAG (0x42000418) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CS_STATUS (0x4200041A) /**< \brief (SERCOM0) I2CS Status */
#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) I2CS Synchronization Busy */
#define REG_SERCOM0_I2CS_ADDR (0x42000424) /**< \brief (SERCOM0) I2CS Address */
#define REG_SERCOM0_I2CS_DATA (0x42000428) /**< \brief (SERCOM0) I2CS Data */
#define REG_SERCOM0_SPI_CTRLA (0x42000400) /**< \brief (SERCOM0) SPI Control A */
#define REG_SERCOM0_SPI_CTRLB (0x42000404) /**< \brief (SERCOM0) SPI Control B */
#define REG_SERCOM0_SPI_BAUD (0x4200040C) /**< \brief (SERCOM0) SPI Baud Rate */
#define REG_SERCOM0_SPI_INTENCLR (0x42000414) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
#define REG_SERCOM0_SPI_INTENSET (0x42000416) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
#define REG_SERCOM0_SPI_INTFLAG (0x42000418) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM0_SPI_STATUS (0x4200041A) /**< \brief (SERCOM0) SPI Status */
#define REG_SERCOM0_SPI_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) SPI Synchronization Busy */
#define REG_SERCOM0_SPI_ADDR (0x42000424) /**< \brief (SERCOM0) SPI Address */
#define REG_SERCOM0_SPI_DATA (0x42000428) /**< \brief (SERCOM0) SPI Data */
#define REG_SERCOM0_SPI_DBGCTRL (0x42000430) /**< \brief (SERCOM0) SPI Debug Control */
#define REG_SERCOM0_USART_CTRLA (0x42000400) /**< \brief (SERCOM0) USART Control A */
#define REG_SERCOM0_USART_CTRLB (0x42000404) /**< \brief (SERCOM0) USART Control B */
#define REG_SERCOM0_USART_CTRLC (0x42000408) /**< \brief (SERCOM0) USART Control C */
#define REG_SERCOM0_USART_BAUD (0x4200040C) /**< \brief (SERCOM0) USART Baud Rate */
#define REG_SERCOM0_USART_RXPL (0x4200040E) /**< \brief (SERCOM0) USART Receive Pulse Length */
#define REG_SERCOM0_USART_INTENCLR (0x42000414) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
#define REG_SERCOM0_USART_INTENSET (0x42000416) /**< \brief (SERCOM0) USART Interrupt Enable Set */
#define REG_SERCOM0_USART_INTFLAG (0x42000418) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
#define REG_SERCOM0_USART_STATUS (0x4200041A) /**< \brief (SERCOM0) USART Status */
#define REG_SERCOM0_USART_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) USART Synchronization Busy */
#define REG_SERCOM0_USART_DATA (0x42000428) /**< \brief (SERCOM0) USART Data */
#define REG_SERCOM0_USART_DBGCTRL (0x42000430) /**< \brief (SERCOM0) USART Debug Control */
#else
#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) I2CM Control A */
#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) I2CM Control B */
#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200040CUL) /**< \brief (SERCOM0) I2CM Baud Rate */
#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) I2CM Status */
#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) I2CM Synchronization Busy */
#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) I2CM Address */
#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000428UL) /**< \brief (SERCOM0) I2CM Data */
#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) I2CM Debug Control */
#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) I2CS Control A */
#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) I2CS Control B */
#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) I2CS Status */
#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) I2CS Synchronization Busy */
#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) I2CS Address */
#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000428UL) /**< \brief (SERCOM0) I2CS Data */
#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) SPI Control A */
#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) SPI Control B */
#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200040CUL) /**< \brief (SERCOM0) SPI Baud Rate */
#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) SPI Status */
#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) SPI Synchronization Busy */
#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) SPI Address */
#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000428UL) /**< \brief (SERCOM0) SPI Data */
#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) SPI Debug Control */
#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) USART Control A */
#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) USART Control B */
#define REG_SERCOM0_USART_CTRLC (*(RwReg *)0x42000408UL) /**< \brief (SERCOM0) USART Control C */
#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200040CUL) /**< \brief (SERCOM0) USART Baud Rate */
#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200040EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */
#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */
#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) USART Status */
#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) USART Synchronization Busy */
#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000428UL) /**< \brief (SERCOM0) USART Data */
#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM0 peripheral ========== */
#define SERCOM0_DMAC_ID_RX 2 // Index of DMA RX trigger
#define SERCOM0_DMAC_ID_TX 3 // Index of DMA TX trigger
#define SERCOM0_GCLK_ID_CORE 19
#define SERCOM0_GCLK_ID_SLOW 18
#define SERCOM0_INT_MSB 6
#define SERCOM0_PMSB 3
#endif /* _SAMC21_SERCOM0_INSTANCE_ */

132
lib/samc21/samc21/include/instance/sercom1.h Normal file
View File

@@ -0,0 +1,132 @@
/**
* \file
*
* \brief Instance description for SERCOM1
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SERCOM1_INSTANCE_
#define _SAMC21_SERCOM1_INSTANCE_
/* ========== Register definition for SERCOM1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM1_I2CM_CTRLA (0x42000800) /**< \brief (SERCOM1) I2CM Control A */
#define REG_SERCOM1_I2CM_CTRLB (0x42000804) /**< \brief (SERCOM1) I2CM Control B */
#define REG_SERCOM1_I2CM_BAUD (0x4200080C) /**< \brief (SERCOM1) I2CM Baud Rate */
#define REG_SERCOM1_I2CM_INTENCLR (0x42000814) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
#define REG_SERCOM1_I2CM_INTENSET (0x42000816) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
#define REG_SERCOM1_I2CM_INTFLAG (0x42000818) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CM_STATUS (0x4200081A) /**< \brief (SERCOM1) I2CM Status */
#define REG_SERCOM1_I2CM_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) I2CM Synchronization Busy */
#define REG_SERCOM1_I2CM_ADDR (0x42000824) /**< \brief (SERCOM1) I2CM Address */
#define REG_SERCOM1_I2CM_DATA (0x42000828) /**< \brief (SERCOM1) I2CM Data */
#define REG_SERCOM1_I2CM_DBGCTRL (0x42000830) /**< \brief (SERCOM1) I2CM Debug Control */
#define REG_SERCOM1_I2CS_CTRLA (0x42000800) /**< \brief (SERCOM1) I2CS Control A */
#define REG_SERCOM1_I2CS_CTRLB (0x42000804) /**< \brief (SERCOM1) I2CS Control B */
#define REG_SERCOM1_I2CS_INTENCLR (0x42000814) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
#define REG_SERCOM1_I2CS_INTENSET (0x42000816) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
#define REG_SERCOM1_I2CS_INTFLAG (0x42000818) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CS_STATUS (0x4200081A) /**< \brief (SERCOM1) I2CS Status */
#define REG_SERCOM1_I2CS_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) I2CS Synchronization Busy */
#define REG_SERCOM1_I2CS_ADDR (0x42000824) /**< \brief (SERCOM1) I2CS Address */
#define REG_SERCOM1_I2CS_DATA (0x42000828) /**< \brief (SERCOM1) I2CS Data */
#define REG_SERCOM1_SPI_CTRLA (0x42000800) /**< \brief (SERCOM1) SPI Control A */
#define REG_SERCOM1_SPI_CTRLB (0x42000804) /**< \brief (SERCOM1) SPI Control B */
#define REG_SERCOM1_SPI_BAUD (0x4200080C) /**< \brief (SERCOM1) SPI Baud Rate */
#define REG_SERCOM1_SPI_INTENCLR (0x42000814) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
#define REG_SERCOM1_SPI_INTENSET (0x42000816) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
#define REG_SERCOM1_SPI_INTFLAG (0x42000818) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM1_SPI_STATUS (0x4200081A) /**< \brief (SERCOM1) SPI Status */
#define REG_SERCOM1_SPI_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) SPI Synchronization Busy */
#define REG_SERCOM1_SPI_ADDR (0x42000824) /**< \brief (SERCOM1) SPI Address */
#define REG_SERCOM1_SPI_DATA (0x42000828) /**< \brief (SERCOM1) SPI Data */
#define REG_SERCOM1_SPI_DBGCTRL (0x42000830) /**< \brief (SERCOM1) SPI Debug Control */
#define REG_SERCOM1_USART_CTRLA (0x42000800) /**< \brief (SERCOM1) USART Control A */
#define REG_SERCOM1_USART_CTRLB (0x42000804) /**< \brief (SERCOM1) USART Control B */
#define REG_SERCOM1_USART_CTRLC (0x42000808) /**< \brief (SERCOM1) USART Control C */
#define REG_SERCOM1_USART_BAUD (0x4200080C) /**< \brief (SERCOM1) USART Baud Rate */
#define REG_SERCOM1_USART_RXPL (0x4200080E) /**< \brief (SERCOM1) USART Receive Pulse Length */
#define REG_SERCOM1_USART_INTENCLR (0x42000814) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
#define REG_SERCOM1_USART_INTENSET (0x42000816) /**< \brief (SERCOM1) USART Interrupt Enable Set */
#define REG_SERCOM1_USART_INTFLAG (0x42000818) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
#define REG_SERCOM1_USART_STATUS (0x4200081A) /**< \brief (SERCOM1) USART Status */
#define REG_SERCOM1_USART_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) USART Synchronization Busy */
#define REG_SERCOM1_USART_DATA (0x42000828) /**< \brief (SERCOM1) USART Data */
#define REG_SERCOM1_USART_DBGCTRL (0x42000830) /**< \brief (SERCOM1) USART Debug Control */
#else
#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) I2CM Control A */
#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) I2CM Control B */
#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4200080CUL) /**< \brief (SERCOM1) I2CM Baud Rate */
#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) I2CM Status */
#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) I2CM Synchronization Busy */
#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) I2CM Address */
#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM1) I2CM Data */
#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) I2CM Debug Control */
#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) I2CS Control A */
#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) I2CS Control B */
#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) I2CS Status */
#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) I2CS Synchronization Busy */
#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) I2CS Address */
#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM1) I2CS Data */
#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) SPI Control A */
#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) SPI Control B */
#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM1) SPI Baud Rate */
#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) SPI Status */
#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) SPI Synchronization Busy */
#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) SPI Address */
#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000828UL) /**< \brief (SERCOM1) SPI Data */
#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) SPI Debug Control */
#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) USART Control A */
#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) USART Control B */
#define REG_SERCOM1_USART_CTRLC (*(RwReg *)0x42000808UL) /**< \brief (SERCOM1) USART Control C */
#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4200080CUL) /**< \brief (SERCOM1) USART Baud Rate */
#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */
#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */
#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) USART Status */
#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) USART Synchronization Busy */
#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000828UL) /**< \brief (SERCOM1) USART Data */
#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM1 peripheral ========== */
#define SERCOM1_DMAC_ID_RX 4 // Index of DMA RX trigger
#define SERCOM1_DMAC_ID_TX 5 // Index of DMA TX trigger
#define SERCOM1_GCLK_ID_CORE 20
#define SERCOM1_GCLK_ID_SLOW 18
#define SERCOM1_INT_MSB 6
#define SERCOM1_PMSB 3
#endif /* _SAMC21_SERCOM1_INSTANCE_ */

132
lib/samc21/samc21/include/instance/sercom2.h Normal file
View File

@@ -0,0 +1,132 @@
/**
* \file
*
* \brief Instance description for SERCOM2
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SERCOM2_INSTANCE_
#define _SAMC21_SERCOM2_INSTANCE_
/* ========== Register definition for SERCOM2 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM2_I2CM_CTRLA (0x42000C00) /**< \brief (SERCOM2) I2CM Control A */
#define REG_SERCOM2_I2CM_CTRLB (0x42000C04) /**< \brief (SERCOM2) I2CM Control B */
#define REG_SERCOM2_I2CM_BAUD (0x42000C0C) /**< \brief (SERCOM2) I2CM Baud Rate */
#define REG_SERCOM2_I2CM_INTENCLR (0x42000C14) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
#define REG_SERCOM2_I2CM_INTENSET (0x42000C16) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
#define REG_SERCOM2_I2CM_INTFLAG (0x42000C18) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM2_I2CM_STATUS (0x42000C1A) /**< \brief (SERCOM2) I2CM Status */
#define REG_SERCOM2_I2CM_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) I2CM Synchronization Busy */
#define REG_SERCOM2_I2CM_ADDR (0x42000C24) /**< \brief (SERCOM2) I2CM Address */
#define REG_SERCOM2_I2CM_DATA (0x42000C28) /**< \brief (SERCOM2) I2CM Data */
#define REG_SERCOM2_I2CM_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) I2CM Debug Control */
#define REG_SERCOM2_I2CS_CTRLA (0x42000C00) /**< \brief (SERCOM2) I2CS Control A */
#define REG_SERCOM2_I2CS_CTRLB (0x42000C04) /**< \brief (SERCOM2) I2CS Control B */
#define REG_SERCOM2_I2CS_INTENCLR (0x42000C14) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
#define REG_SERCOM2_I2CS_INTENSET (0x42000C16) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
#define REG_SERCOM2_I2CS_INTFLAG (0x42000C18) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM2_I2CS_STATUS (0x42000C1A) /**< \brief (SERCOM2) I2CS Status */
#define REG_SERCOM2_I2CS_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) I2CS Synchronization Busy */
#define REG_SERCOM2_I2CS_ADDR (0x42000C24) /**< \brief (SERCOM2) I2CS Address */
#define REG_SERCOM2_I2CS_DATA (0x42000C28) /**< \brief (SERCOM2) I2CS Data */
#define REG_SERCOM2_SPI_CTRLA (0x42000C00) /**< \brief (SERCOM2) SPI Control A */
#define REG_SERCOM2_SPI_CTRLB (0x42000C04) /**< \brief (SERCOM2) SPI Control B */
#define REG_SERCOM2_SPI_BAUD (0x42000C0C) /**< \brief (SERCOM2) SPI Baud Rate */
#define REG_SERCOM2_SPI_INTENCLR (0x42000C14) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
#define REG_SERCOM2_SPI_INTENSET (0x42000C16) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
#define REG_SERCOM2_SPI_INTFLAG (0x42000C18) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM2_SPI_STATUS (0x42000C1A) /**< \brief (SERCOM2) SPI Status */
#define REG_SERCOM2_SPI_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) SPI Synchronization Busy */
#define REG_SERCOM2_SPI_ADDR (0x42000C24) /**< \brief (SERCOM2) SPI Address */
#define REG_SERCOM2_SPI_DATA (0x42000C28) /**< \brief (SERCOM2) SPI Data */
#define REG_SERCOM2_SPI_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) SPI Debug Control */
#define REG_SERCOM2_USART_CTRLA (0x42000C00) /**< \brief (SERCOM2) USART Control A */
#define REG_SERCOM2_USART_CTRLB (0x42000C04) /**< \brief (SERCOM2) USART Control B */
#define REG_SERCOM2_USART_CTRLC (0x42000C08) /**< \brief (SERCOM2) USART Control C */
#define REG_SERCOM2_USART_BAUD (0x42000C0C) /**< \brief (SERCOM2) USART Baud Rate */
#define REG_SERCOM2_USART_RXPL (0x42000C0E) /**< \brief (SERCOM2) USART Receive Pulse Length */
#define REG_SERCOM2_USART_INTENCLR (0x42000C14) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
#define REG_SERCOM2_USART_INTENSET (0x42000C16) /**< \brief (SERCOM2) USART Interrupt Enable Set */
#define REG_SERCOM2_USART_INTFLAG (0x42000C18) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
#define REG_SERCOM2_USART_STATUS (0x42000C1A) /**< \brief (SERCOM2) USART Status */
#define REG_SERCOM2_USART_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) USART Synchronization Busy */
#define REG_SERCOM2_USART_DATA (0x42000C28) /**< \brief (SERCOM2) USART Data */
#define REG_SERCOM2_USART_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) USART Debug Control */
#else
#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) I2CM Control A */
#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) I2CM Control B */
#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x42000C0CUL) /**< \brief (SERCOM2) I2CM Baud Rate */
#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) I2CM Status */
#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) I2CM Synchronization Busy */
#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) I2CM Address */
#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM2) I2CM Data */
#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) I2CM Debug Control */
#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) I2CS Control A */
#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) I2CS Control B */
#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) I2CS Status */
#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) I2CS Synchronization Busy */
#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) I2CS Address */
#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM2) I2CS Data */
#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) SPI Control A */
#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) SPI Control B */
#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM2) SPI Baud Rate */
#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) SPI Status */
#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) SPI Synchronization Busy */
#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) SPI Address */
#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42000C28UL) /**< \brief (SERCOM2) SPI Data */
#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) SPI Debug Control */
#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) USART Control A */
#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) USART Control B */
#define REG_SERCOM2_USART_CTRLC (*(RwReg *)0x42000C08UL) /**< \brief (SERCOM2) USART Control C */
#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x42000C0CUL) /**< \brief (SERCOM2) USART Baud Rate */
#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM2) USART Receive Pulse Length */
#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) USART Interrupt Enable Set */
#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) USART Status */
#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) USART Synchronization Busy */
#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42000C28UL) /**< \brief (SERCOM2) USART Data */
#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM2 peripheral ========== */
#define SERCOM2_DMAC_ID_RX 6 // Index of DMA RX trigger
#define SERCOM2_DMAC_ID_TX 7 // Index of DMA TX trigger
#define SERCOM2_GCLK_ID_CORE 21
#define SERCOM2_GCLK_ID_SLOW 18
#define SERCOM2_INT_MSB 6
#define SERCOM2_PMSB 3
#endif /* _SAMC21_SERCOM2_INSTANCE_ */

132
lib/samc21/samc21/include/instance/sercom3.h Normal file
View File

@@ -0,0 +1,132 @@
/**
* \file
*
* \brief Instance description for SERCOM3
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SERCOM3_INSTANCE_
#define _SAMC21_SERCOM3_INSTANCE_
/* ========== Register definition for SERCOM3 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM3_I2CM_CTRLA (0x42001000) /**< \brief (SERCOM3) I2CM Control A */
#define REG_SERCOM3_I2CM_CTRLB (0x42001004) /**< \brief (SERCOM3) I2CM Control B */
#define REG_SERCOM3_I2CM_BAUD (0x4200100C) /**< \brief (SERCOM3) I2CM Baud Rate */
#define REG_SERCOM3_I2CM_INTENCLR (0x42001014) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
#define REG_SERCOM3_I2CM_INTENSET (0x42001016) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
#define REG_SERCOM3_I2CM_INTFLAG (0x42001018) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM3_I2CM_STATUS (0x4200101A) /**< \brief (SERCOM3) I2CM Status */
#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) I2CM Synchronization Busy */
#define REG_SERCOM3_I2CM_ADDR (0x42001024) /**< \brief (SERCOM3) I2CM Address */
#define REG_SERCOM3_I2CM_DATA (0x42001028) /**< \brief (SERCOM3) I2CM Data */
#define REG_SERCOM3_I2CM_DBGCTRL (0x42001030) /**< \brief (SERCOM3) I2CM Debug Control */
#define REG_SERCOM3_I2CS_CTRLA (0x42001000) /**< \brief (SERCOM3) I2CS Control A */
#define REG_SERCOM3_I2CS_CTRLB (0x42001004) /**< \brief (SERCOM3) I2CS Control B */
#define REG_SERCOM3_I2CS_INTENCLR (0x42001014) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
#define REG_SERCOM3_I2CS_INTENSET (0x42001016) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
#define REG_SERCOM3_I2CS_INTFLAG (0x42001018) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM3_I2CS_STATUS (0x4200101A) /**< \brief (SERCOM3) I2CS Status */
#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) I2CS Synchronization Busy */
#define REG_SERCOM3_I2CS_ADDR (0x42001024) /**< \brief (SERCOM3) I2CS Address */
#define REG_SERCOM3_I2CS_DATA (0x42001028) /**< \brief (SERCOM3) I2CS Data */
#define REG_SERCOM3_SPI_CTRLA (0x42001000) /**< \brief (SERCOM3) SPI Control A */
#define REG_SERCOM3_SPI_CTRLB (0x42001004) /**< \brief (SERCOM3) SPI Control B */
#define REG_SERCOM3_SPI_BAUD (0x4200100C) /**< \brief (SERCOM3) SPI Baud Rate */
#define REG_SERCOM3_SPI_INTENCLR (0x42001014) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
#define REG_SERCOM3_SPI_INTENSET (0x42001016) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
#define REG_SERCOM3_SPI_INTFLAG (0x42001018) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM3_SPI_STATUS (0x4200101A) /**< \brief (SERCOM3) SPI Status */
#define REG_SERCOM3_SPI_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) SPI Synchronization Busy */
#define REG_SERCOM3_SPI_ADDR (0x42001024) /**< \brief (SERCOM3) SPI Address */
#define REG_SERCOM3_SPI_DATA (0x42001028) /**< \brief (SERCOM3) SPI Data */
#define REG_SERCOM3_SPI_DBGCTRL (0x42001030) /**< \brief (SERCOM3) SPI Debug Control */
#define REG_SERCOM3_USART_CTRLA (0x42001000) /**< \brief (SERCOM3) USART Control A */
#define REG_SERCOM3_USART_CTRLB (0x42001004) /**< \brief (SERCOM3) USART Control B */
#define REG_SERCOM3_USART_CTRLC (0x42001008) /**< \brief (SERCOM3) USART Control C */
#define REG_SERCOM3_USART_BAUD (0x4200100C) /**< \brief (SERCOM3) USART Baud Rate */
#define REG_SERCOM3_USART_RXPL (0x4200100E) /**< \brief (SERCOM3) USART Receive Pulse Length */
#define REG_SERCOM3_USART_INTENCLR (0x42001014) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
#define REG_SERCOM3_USART_INTENSET (0x42001016) /**< \brief (SERCOM3) USART Interrupt Enable Set */
#define REG_SERCOM3_USART_INTFLAG (0x42001018) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
#define REG_SERCOM3_USART_STATUS (0x4200101A) /**< \brief (SERCOM3) USART Status */
#define REG_SERCOM3_USART_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) USART Synchronization Busy */
#define REG_SERCOM3_USART_DATA (0x42001028) /**< \brief (SERCOM3) USART Data */
#define REG_SERCOM3_USART_DBGCTRL (0x42001030) /**< \brief (SERCOM3) USART Debug Control */
#else
#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) I2CM Control A */
#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) I2CM Control B */
#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200100CUL) /**< \brief (SERCOM3) I2CM Baud Rate */
#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) I2CM Status */
#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) I2CM Synchronization Busy */
#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) I2CM Address */
#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM3) I2CM Data */
#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) I2CM Debug Control */
#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) I2CS Control A */
#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) I2CS Control B */
#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) I2CS Status */
#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) I2CS Synchronization Busy */
#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) I2CS Address */
#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM3) I2CS Data */
#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) SPI Control A */
#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) SPI Control B */
#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM3) SPI Baud Rate */
#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) SPI Status */
#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) SPI Synchronization Busy */
#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) SPI Address */
#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001028UL) /**< \brief (SERCOM3) SPI Data */
#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) SPI Debug Control */
#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) USART Control A */
#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) USART Control B */
#define REG_SERCOM3_USART_CTRLC (*(RwReg *)0x42001008UL) /**< \brief (SERCOM3) USART Control C */
#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200100CUL) /**< \brief (SERCOM3) USART Baud Rate */
#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */
#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */
#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) USART Status */
#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) USART Synchronization Busy */
#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001028UL) /**< \brief (SERCOM3) USART Data */
#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM3 peripheral ========== */
#define SERCOM3_DMAC_ID_RX 8 // Index of DMA RX trigger
#define SERCOM3_DMAC_ID_TX 9 // Index of DMA TX trigger
#define SERCOM3_GCLK_ID_CORE 22
#define SERCOM3_GCLK_ID_SLOW 18
#define SERCOM3_INT_MSB 6
#define SERCOM3_PMSB 3
#endif /* _SAMC21_SERCOM3_INSTANCE_ */

132
lib/samc21/samc21/include/instance/sercom4.h Normal file
View File

@@ -0,0 +1,132 @@
/**
* \file
*
* \brief Instance description for SERCOM4
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SERCOM4_INSTANCE_
#define _SAMC21_SERCOM4_INSTANCE_
/* ========== Register definition for SERCOM4 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM4_I2CM_CTRLA (0x42001400) /**< \brief (SERCOM4) I2CM Control A */
#define REG_SERCOM4_I2CM_CTRLB (0x42001404) /**< \brief (SERCOM4) I2CM Control B */
#define REG_SERCOM4_I2CM_BAUD (0x4200140C) /**< \brief (SERCOM4) I2CM Baud Rate */
#define REG_SERCOM4_I2CM_INTENCLR (0x42001414) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
#define REG_SERCOM4_I2CM_INTENSET (0x42001416) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
#define REG_SERCOM4_I2CM_INTFLAG (0x42001418) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM4_I2CM_STATUS (0x4200141A) /**< \brief (SERCOM4) I2CM Status */
#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) I2CM Synchronization Busy */
#define REG_SERCOM4_I2CM_ADDR (0x42001424) /**< \brief (SERCOM4) I2CM Address */
#define REG_SERCOM4_I2CM_DATA (0x42001428) /**< \brief (SERCOM4) I2CM Data */
#define REG_SERCOM4_I2CM_DBGCTRL (0x42001430) /**< \brief (SERCOM4) I2CM Debug Control */
#define REG_SERCOM4_I2CS_CTRLA (0x42001400) /**< \brief (SERCOM4) I2CS Control A */
#define REG_SERCOM4_I2CS_CTRLB (0x42001404) /**< \brief (SERCOM4) I2CS Control B */
#define REG_SERCOM4_I2CS_INTENCLR (0x42001414) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
#define REG_SERCOM4_I2CS_INTENSET (0x42001416) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
#define REG_SERCOM4_I2CS_INTFLAG (0x42001418) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM4_I2CS_STATUS (0x4200141A) /**< \brief (SERCOM4) I2CS Status */
#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) I2CS Synchronization Busy */
#define REG_SERCOM4_I2CS_ADDR (0x42001424) /**< \brief (SERCOM4) I2CS Address */
#define REG_SERCOM4_I2CS_DATA (0x42001428) /**< \brief (SERCOM4) I2CS Data */
#define REG_SERCOM4_SPI_CTRLA (0x42001400) /**< \brief (SERCOM4) SPI Control A */
#define REG_SERCOM4_SPI_CTRLB (0x42001404) /**< \brief (SERCOM4) SPI Control B */
#define REG_SERCOM4_SPI_BAUD (0x4200140C) /**< \brief (SERCOM4) SPI Baud Rate */
#define REG_SERCOM4_SPI_INTENCLR (0x42001414) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
#define REG_SERCOM4_SPI_INTENSET (0x42001416) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
#define REG_SERCOM4_SPI_INTFLAG (0x42001418) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM4_SPI_STATUS (0x4200141A) /**< \brief (SERCOM4) SPI Status */
#define REG_SERCOM4_SPI_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) SPI Synchronization Busy */
#define REG_SERCOM4_SPI_ADDR (0x42001424) /**< \brief (SERCOM4) SPI Address */
#define REG_SERCOM4_SPI_DATA (0x42001428) /**< \brief (SERCOM4) SPI Data */
#define REG_SERCOM4_SPI_DBGCTRL (0x42001430) /**< \brief (SERCOM4) SPI Debug Control */
#define REG_SERCOM4_USART_CTRLA (0x42001400) /**< \brief (SERCOM4) USART Control A */
#define REG_SERCOM4_USART_CTRLB (0x42001404) /**< \brief (SERCOM4) USART Control B */
#define REG_SERCOM4_USART_CTRLC (0x42001408) /**< \brief (SERCOM4) USART Control C */
#define REG_SERCOM4_USART_BAUD (0x4200140C) /**< \brief (SERCOM4) USART Baud Rate */
#define REG_SERCOM4_USART_RXPL (0x4200140E) /**< \brief (SERCOM4) USART Receive Pulse Length */
#define REG_SERCOM4_USART_INTENCLR (0x42001414) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
#define REG_SERCOM4_USART_INTENSET (0x42001416) /**< \brief (SERCOM4) USART Interrupt Enable Set */
#define REG_SERCOM4_USART_INTFLAG (0x42001418) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
#define REG_SERCOM4_USART_STATUS (0x4200141A) /**< \brief (SERCOM4) USART Status */
#define REG_SERCOM4_USART_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) USART Synchronization Busy */
#define REG_SERCOM4_USART_DATA (0x42001428) /**< \brief (SERCOM4) USART Data */
#define REG_SERCOM4_USART_DBGCTRL (0x42001430) /**< \brief (SERCOM4) USART Debug Control */
#else
#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) I2CM Control A */
#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) I2CM Control B */
#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200140CUL) /**< \brief (SERCOM4) I2CM Baud Rate */
#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) I2CM Status */
#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) I2CM Synchronization Busy */
#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) I2CM Address */
#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM4) I2CM Data */
#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) I2CM Debug Control */
#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) I2CS Control A */
#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) I2CS Control B */
#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) I2CS Status */
#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) I2CS Synchronization Busy */
#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) I2CS Address */
#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM4) I2CS Data */
#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) SPI Control A */
#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) SPI Control B */
#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM4) SPI Baud Rate */
#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) SPI Status */
#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) SPI Synchronization Busy */
#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) SPI Address */
#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001428UL) /**< \brief (SERCOM4) SPI Data */
#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) SPI Debug Control */
#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) USART Control A */
#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) USART Control B */
#define REG_SERCOM4_USART_CTRLC (*(RwReg *)0x42001408UL) /**< \brief (SERCOM4) USART Control C */
#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200140CUL) /**< \brief (SERCOM4) USART Baud Rate */
#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM4) USART Receive Pulse Length */
#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) USART Interrupt Enable Set */
#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) USART Status */
#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) USART Synchronization Busy */
#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001428UL) /**< \brief (SERCOM4) USART Data */
#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM4 peripheral ========== */
#define SERCOM4_DMAC_ID_RX 10 // Index of DMA RX trigger
#define SERCOM4_DMAC_ID_TX 11 // Index of DMA TX trigger
#define SERCOM4_GCLK_ID_CORE 23
#define SERCOM4_GCLK_ID_SLOW 18
#define SERCOM4_INT_MSB 6
#define SERCOM4_PMSB 3
#endif /* _SAMC21_SERCOM4_INSTANCE_ */

132
lib/samc21/samc21/include/instance/sercom5.h Normal file
View File

@@ -0,0 +1,132 @@
/**
* \file
*
* \brief Instance description for SERCOM5
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SERCOM5_INSTANCE_
#define _SAMC21_SERCOM5_INSTANCE_
/* ========== Register definition for SERCOM5 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM5_I2CM_CTRLA (0x42001800) /**< \brief (SERCOM5) I2CM Control A */
#define REG_SERCOM5_I2CM_CTRLB (0x42001804) /**< \brief (SERCOM5) I2CM Control B */
#define REG_SERCOM5_I2CM_BAUD (0x4200180C) /**< \brief (SERCOM5) I2CM Baud Rate */
#define REG_SERCOM5_I2CM_INTENCLR (0x42001814) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
#define REG_SERCOM5_I2CM_INTENSET (0x42001816) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
#define REG_SERCOM5_I2CM_INTFLAG (0x42001818) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM5_I2CM_STATUS (0x4200181A) /**< \brief (SERCOM5) I2CM Status */
#define REG_SERCOM5_I2CM_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) I2CM Synchronization Busy */
#define REG_SERCOM5_I2CM_ADDR (0x42001824) /**< \brief (SERCOM5) I2CM Address */
#define REG_SERCOM5_I2CM_DATA (0x42001828) /**< \brief (SERCOM5) I2CM Data */
#define REG_SERCOM5_I2CM_DBGCTRL (0x42001830) /**< \brief (SERCOM5) I2CM Debug Control */
#define REG_SERCOM5_I2CS_CTRLA (0x42001800) /**< \brief (SERCOM5) I2CS Control A */
#define REG_SERCOM5_I2CS_CTRLB (0x42001804) /**< \brief (SERCOM5) I2CS Control B */
#define REG_SERCOM5_I2CS_INTENCLR (0x42001814) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
#define REG_SERCOM5_I2CS_INTENSET (0x42001816) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
#define REG_SERCOM5_I2CS_INTFLAG (0x42001818) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM5_I2CS_STATUS (0x4200181A) /**< \brief (SERCOM5) I2CS Status */
#define REG_SERCOM5_I2CS_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) I2CS Synchronization Busy */
#define REG_SERCOM5_I2CS_ADDR (0x42001824) /**< \brief (SERCOM5) I2CS Address */
#define REG_SERCOM5_I2CS_DATA (0x42001828) /**< \brief (SERCOM5) I2CS Data */
#define REG_SERCOM5_SPI_CTRLA (0x42001800) /**< \brief (SERCOM5) SPI Control A */
#define REG_SERCOM5_SPI_CTRLB (0x42001804) /**< \brief (SERCOM5) SPI Control B */
#define REG_SERCOM5_SPI_BAUD (0x4200180C) /**< \brief (SERCOM5) SPI Baud Rate */
#define REG_SERCOM5_SPI_INTENCLR (0x42001814) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
#define REG_SERCOM5_SPI_INTENSET (0x42001816) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
#define REG_SERCOM5_SPI_INTFLAG (0x42001818) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM5_SPI_STATUS (0x4200181A) /**< \brief (SERCOM5) SPI Status */
#define REG_SERCOM5_SPI_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) SPI Synchronization Busy */
#define REG_SERCOM5_SPI_ADDR (0x42001824) /**< \brief (SERCOM5) SPI Address */
#define REG_SERCOM5_SPI_DATA (0x42001828) /**< \brief (SERCOM5) SPI Data */
#define REG_SERCOM5_SPI_DBGCTRL (0x42001830) /**< \brief (SERCOM5) SPI Debug Control */
#define REG_SERCOM5_USART_CTRLA (0x42001800) /**< \brief (SERCOM5) USART Control A */
#define REG_SERCOM5_USART_CTRLB (0x42001804) /**< \brief (SERCOM5) USART Control B */
#define REG_SERCOM5_USART_CTRLC (0x42001808) /**< \brief (SERCOM5) USART Control C */
#define REG_SERCOM5_USART_BAUD (0x4200180C) /**< \brief (SERCOM5) USART Baud Rate */
#define REG_SERCOM5_USART_RXPL (0x4200180E) /**< \brief (SERCOM5) USART Receive Pulse Length */
#define REG_SERCOM5_USART_INTENCLR (0x42001814) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
#define REG_SERCOM5_USART_INTENSET (0x42001816) /**< \brief (SERCOM5) USART Interrupt Enable Set */
#define REG_SERCOM5_USART_INTFLAG (0x42001818) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
#define REG_SERCOM5_USART_STATUS (0x4200181A) /**< \brief (SERCOM5) USART Status */
#define REG_SERCOM5_USART_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) USART Synchronization Busy */
#define REG_SERCOM5_USART_DATA (0x42001828) /**< \brief (SERCOM5) USART Data */
#define REG_SERCOM5_USART_DBGCTRL (0x42001830) /**< \brief (SERCOM5) USART Debug Control */
#else
#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) I2CM Control A */
#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) I2CM Control B */
#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x4200180CUL) /**< \brief (SERCOM5) I2CM Baud Rate */
#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) I2CM Status */
#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) I2CM Synchronization Busy */
#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) I2CM Address */
#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM5) I2CM Data */
#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) I2CM Debug Control */
#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) I2CS Control A */
#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) I2CS Control B */
#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) I2CS Status */
#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) I2CS Synchronization Busy */
#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) I2CS Address */
#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM5) I2CS Data */
#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) SPI Control A */
#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) SPI Control B */
#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM5) SPI Baud Rate */
#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) SPI Status */
#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) SPI Synchronization Busy */
#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) SPI Address */
#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001828UL) /**< \brief (SERCOM5) SPI Data */
#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) SPI Debug Control */
#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) USART Control A */
#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) USART Control B */
#define REG_SERCOM5_USART_CTRLC (*(RwReg *)0x42001808UL) /**< \brief (SERCOM5) USART Control C */
#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x4200180CUL) /**< \brief (SERCOM5) USART Baud Rate */
#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */
#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */
#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) USART Status */
#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) USART Synchronization Busy */
#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001828UL) /**< \brief (SERCOM5) USART Data */
#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM5 peripheral ========== */
#define SERCOM5_DMAC_ID_RX 12 // Index of DMA RX trigger
#define SERCOM5_DMAC_ID_TX 13 // Index of DMA TX trigger
#define SERCOM5_GCLK_ID_CORE 25
#define SERCOM5_GCLK_ID_SLOW 24
#define SERCOM5_INT_MSB 6
#define SERCOM5_PMSB 3
#endif /* _SAMC21_SERCOM5_INSTANCE_ */

59
lib/samc21/samc21/include/instance/supc.h Normal file
View File

@@ -0,0 +1,59 @@
/**
* \file
*
* \brief Instance description for SUPC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SUPC_INSTANCE_
#define _SAMC21_SUPC_INSTANCE_
/* ========== Register definition for SUPC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SUPC_INTENCLR (0x40001800) /**< \brief (SUPC) Interrupt Enable Clear */
#define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */
#define REG_SUPC_INTFLAG (0x40001808) /**< \brief (SUPC) Interrupt Flag Status and Clear */
#define REG_SUPC_STATUS (0x4000180C) /**< \brief (SUPC) Power and Clocks Status */
#define REG_SUPC_BODVDD (0x40001810) /**< \brief (SUPC) BODVDD Control */
#define REG_SUPC_BODCORE (0x40001814) /**< \brief (SUPC) BODCORE Control */
#define REG_SUPC_VREG (0x40001818) /**< \brief (SUPC) VREG Control */
#define REG_SUPC_VREF (0x4000181C) /**< \brief (SUPC) VREF Control */
#else
#define REG_SUPC_INTENCLR (*(RwReg *)0x40001800UL) /**< \brief (SUPC) Interrupt Enable Clear */
#define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Set */
#define REG_SUPC_INTFLAG (*(RwReg *)0x40001808UL) /**< \brief (SUPC) Interrupt Flag Status and Clear */
#define REG_SUPC_STATUS (*(RoReg *)0x4000180CUL) /**< \brief (SUPC) Power and Clocks Status */
#define REG_SUPC_BODVDD (*(RwReg *)0x40001810UL) /**< \brief (SUPC) BODVDD Control */
#define REG_SUPC_BODCORE (*(RwReg *)0x40001814UL) /**< \brief (SUPC) BODCORE Control */
#define REG_SUPC_VREG (*(RwReg *)0x40001818UL) /**< \brief (SUPC) VREG Control */
#define REG_SUPC_VREF (*(RwReg *)0x4000181CUL) /**< \brief (SUPC) VREF Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SUPC peripheral ========== */
#define SUPC_BODCORE_CALIB_MSB 5
#define SUPC_BODVDD_CALIB_MSB 5
#define SUPC_SUPC_OUT_NUM_MSB 1 // MSB of backup output pad Number
#endif /* _SAMC21_SUPC_INSTANCE_ */

109
lib/samc21/samc21/include/instance/tc0.h Normal file
View File

@@ -0,0 +1,109 @@
/**
* \file
*
* \brief Instance description for TC0
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TC0_INSTANCE_
#define _SAMC21_TC0_INSTANCE_
/* ========== Register definition for TC0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC0_CTRLA (0x42003000) /**< \brief (TC0) Control A */
#define REG_TC0_CTRLBCLR (0x42003004) /**< \brief (TC0) Control B Clear */
#define REG_TC0_CTRLBSET (0x42003005) /**< \brief (TC0) Control B Set */
#define REG_TC0_EVCTRL (0x42003006) /**< \brief (TC0) Event Control */
#define REG_TC0_INTENCLR (0x42003008) /**< \brief (TC0) Interrupt Enable Clear */
#define REG_TC0_INTENSET (0x42003009) /**< \brief (TC0) Interrupt Enable Set */
#define REG_TC0_INTFLAG (0x4200300A) /**< \brief (TC0) Interrupt Flag Status and Clear */
#define REG_TC0_STATUS (0x4200300B) /**< \brief (TC0) Status */
#define REG_TC0_WAVE (0x4200300C) /**< \brief (TC0) Waveform Generation Control */
#define REG_TC0_DRVCTRL (0x4200300D) /**< \brief (TC0) Control C */
#define REG_TC0_DBGCTRL (0x4200300F) /**< \brief (TC0) Debug Control */
#define REG_TC0_SYNCBUSY (0x42003010) /**< \brief (TC0) Synchronization Status */
#define REG_TC0_COUNT16_COUNT (0x42003014) /**< \brief (TC0) COUNT16 Count */
#define REG_TC0_COUNT16_CC0 (0x4200301C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
#define REG_TC0_COUNT16_CC1 (0x4200301E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
#define REG_TC0_COUNT16_CCBUF0 (0x42003030) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC0_COUNT16_CCBUF1 (0x42003032) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC0_COUNT32_COUNT (0x42003014) /**< \brief (TC0) COUNT32 Count */
#define REG_TC0_COUNT32_CC0 (0x4200301C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
#define REG_TC0_COUNT32_CC1 (0x42003020) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
#define REG_TC0_COUNT32_CCBUF0 (0x42003030) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC0_COUNT32_CCBUF1 (0x42003034) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC0_COUNT8_COUNT (0x42003014) /**< \brief (TC0) COUNT8 Count */
#define REG_TC0_COUNT8_PER (0x4200301B) /**< \brief (TC0) COUNT8 Period */
#define REG_TC0_COUNT8_CC0 (0x4200301C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
#define REG_TC0_COUNT8_CC1 (0x4200301D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
#define REG_TC0_COUNT8_PERBUF (0x4200302F) /**< \brief (TC0) COUNT8 Period Buffer */
#define REG_TC0_COUNT8_CCBUF0 (0x42003030) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC0_COUNT8_CCBUF1 (0x42003031) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
#else
#define REG_TC0_CTRLA (*(RwReg *)0x42003000UL) /**< \brief (TC0) Control A */
#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42003004UL) /**< \brief (TC0) Control B Clear */
#define REG_TC0_CTRLBSET (*(RwReg8 *)0x42003005UL) /**< \brief (TC0) Control B Set */
#define REG_TC0_EVCTRL (*(RwReg16*)0x42003006UL) /**< \brief (TC0) Event Control */
#define REG_TC0_INTENCLR (*(RwReg8 *)0x42003008UL) /**< \brief (TC0) Interrupt Enable Clear */
#define REG_TC0_INTENSET (*(RwReg8 *)0x42003009UL) /**< \brief (TC0) Interrupt Enable Set */
#define REG_TC0_INTFLAG (*(RwReg8 *)0x4200300AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */
#define REG_TC0_STATUS (*(RwReg8 *)0x4200300BUL) /**< \brief (TC0) Status */
#define REG_TC0_WAVE (*(RwReg8 *)0x4200300CUL) /**< \brief (TC0) Waveform Generation Control */
#define REG_TC0_DRVCTRL (*(RwReg8 *)0x4200300DUL) /**< \brief (TC0) Control C */
#define REG_TC0_DBGCTRL (*(RwReg8 *)0x4200300FUL) /**< \brief (TC0) Debug Control */
#define REG_TC0_SYNCBUSY (*(RoReg *)0x42003010UL) /**< \brief (TC0) Synchronization Status */
#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42003014UL) /**< \brief (TC0) COUNT16 Count */
#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4200301CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200301EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
#define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x42003030UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x42003032UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42003014UL) /**< \brief (TC0) COUNT32 Count */
#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4200301CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x42003020UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
#define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x42003030UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x42003034UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42003014UL) /**< \brief (TC0) COUNT8 Count */
#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4200301BUL) /**< \brief (TC0) COUNT8 Period */
#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4200301CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4200301DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
#define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4200302FUL) /**< \brief (TC0) COUNT8 Period Buffer */
#define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x42003030UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x42003031UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC0 peripheral ========== */
#define TC0_CC_NUM 2
#define TC0_DMAC_ID_MC_0 28
#define TC0_DMAC_ID_MC_1 29
#define TC0_DMAC_ID_MC_LSB 28
#define TC0_DMAC_ID_MC_MSB 29
#define TC0_DMAC_ID_MC_SIZE 2
#define TC0_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger
#define TC0_EXT 0
#define TC0_GCLK_ID 30
#define TC0_MASTER 1
#define TC0_OW_NUM 2
#endif /* _SAMC21_TC0_INSTANCE_ */

109
lib/samc21/samc21/include/instance/tc1.h Normal file
View File

@@ -0,0 +1,109 @@
/**
* \file
*
* \brief Instance description for TC1
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TC1_INSTANCE_
#define _SAMC21_TC1_INSTANCE_
/* ========== Register definition for TC1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC1_CTRLA (0x42003400) /**< \brief (TC1) Control A */
#define REG_TC1_CTRLBCLR (0x42003404) /**< \brief (TC1) Control B Clear */
#define REG_TC1_CTRLBSET (0x42003405) /**< \brief (TC1) Control B Set */
#define REG_TC1_EVCTRL (0x42003406) /**< \brief (TC1) Event Control */
#define REG_TC1_INTENCLR (0x42003408) /**< \brief (TC1) Interrupt Enable Clear */
#define REG_TC1_INTENSET (0x42003409) /**< \brief (TC1) Interrupt Enable Set */
#define REG_TC1_INTFLAG (0x4200340A) /**< \brief (TC1) Interrupt Flag Status and Clear */
#define REG_TC1_STATUS (0x4200340B) /**< \brief (TC1) Status */
#define REG_TC1_WAVE (0x4200340C) /**< \brief (TC1) Waveform Generation Control */
#define REG_TC1_DRVCTRL (0x4200340D) /**< \brief (TC1) Control C */
#define REG_TC1_DBGCTRL (0x4200340F) /**< \brief (TC1) Debug Control */
#define REG_TC1_SYNCBUSY (0x42003410) /**< \brief (TC1) Synchronization Status */
#define REG_TC1_COUNT16_COUNT (0x42003414) /**< \brief (TC1) COUNT16 Count */
#define REG_TC1_COUNT16_CC0 (0x4200341C) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
#define REG_TC1_COUNT16_CC1 (0x4200341E) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
#define REG_TC1_COUNT16_CCBUF0 (0x42003430) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC1_COUNT16_CCBUF1 (0x42003432) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC1_COUNT32_COUNT (0x42003414) /**< \brief (TC1) COUNT32 Count */
#define REG_TC1_COUNT32_CC0 (0x4200341C) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
#define REG_TC1_COUNT32_CC1 (0x42003420) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
#define REG_TC1_COUNT32_CCBUF0 (0x42003430) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC1_COUNT32_CCBUF1 (0x42003434) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC1_COUNT8_COUNT (0x42003414) /**< \brief (TC1) COUNT8 Count */
#define REG_TC1_COUNT8_PER (0x4200341B) /**< \brief (TC1) COUNT8 Period */
#define REG_TC1_COUNT8_CC0 (0x4200341C) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
#define REG_TC1_COUNT8_CC1 (0x4200341D) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
#define REG_TC1_COUNT8_PERBUF (0x4200342F) /**< \brief (TC1) COUNT8 Period Buffer */
#define REG_TC1_COUNT8_CCBUF0 (0x42003430) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC1_COUNT8_CCBUF1 (0x42003431) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
#else
#define REG_TC1_CTRLA (*(RwReg *)0x42003400UL) /**< \brief (TC1) Control A */
#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42003404UL) /**< \brief (TC1) Control B Clear */
#define REG_TC1_CTRLBSET (*(RwReg8 *)0x42003405UL) /**< \brief (TC1) Control B Set */
#define REG_TC1_EVCTRL (*(RwReg16*)0x42003406UL) /**< \brief (TC1) Event Control */
#define REG_TC1_INTENCLR (*(RwReg8 *)0x42003408UL) /**< \brief (TC1) Interrupt Enable Clear */
#define REG_TC1_INTENSET (*(RwReg8 *)0x42003409UL) /**< \brief (TC1) Interrupt Enable Set */
#define REG_TC1_INTFLAG (*(RwReg8 *)0x4200340AUL) /**< \brief (TC1) Interrupt Flag Status and Clear */
#define REG_TC1_STATUS (*(RwReg8 *)0x4200340BUL) /**< \brief (TC1) Status */
#define REG_TC1_WAVE (*(RwReg8 *)0x4200340CUL) /**< \brief (TC1) Waveform Generation Control */
#define REG_TC1_DRVCTRL (*(RwReg8 *)0x4200340DUL) /**< \brief (TC1) Control C */
#define REG_TC1_DBGCTRL (*(RwReg8 *)0x4200340FUL) /**< \brief (TC1) Debug Control */
#define REG_TC1_SYNCBUSY (*(RoReg *)0x42003410UL) /**< \brief (TC1) Synchronization Status */
#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x42003414UL) /**< \brief (TC1) COUNT16 Count */
#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x4200341CUL) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x4200341EUL) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
#define REG_TC1_COUNT16_CCBUF0 (*(RwReg16*)0x42003430UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC1_COUNT16_CCBUF1 (*(RwReg16*)0x42003432UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42003414UL) /**< \brief (TC1) COUNT32 Count */
#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x4200341CUL) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x42003420UL) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
#define REG_TC1_COUNT32_CCBUF0 (*(RwReg *)0x42003430UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC1_COUNT32_CCBUF1 (*(RwReg *)0x42003434UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42003414UL) /**< \brief (TC1) COUNT8 Count */
#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x4200341BUL) /**< \brief (TC1) COUNT8 Period */
#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x4200341CUL) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x4200341DUL) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
#define REG_TC1_COUNT8_PERBUF (*(RwReg8 *)0x4200342FUL) /**< \brief (TC1) COUNT8 Period Buffer */
#define REG_TC1_COUNT8_CCBUF0 (*(RwReg8 *)0x42003430UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC1_COUNT8_CCBUF1 (*(RwReg8 *)0x42003431UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC1 peripheral ========== */
#define TC1_CC_NUM 2
#define TC1_DMAC_ID_MC_0 31
#define TC1_DMAC_ID_MC_1 32
#define TC1_DMAC_ID_MC_LSB 31
#define TC1_DMAC_ID_MC_MSB 32
#define TC1_DMAC_ID_MC_SIZE 2
#define TC1_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
#define TC1_EXT 0
#define TC1_GCLK_ID 30
#define TC1_MASTER 0
#define TC1_OW_NUM 2
#endif /* _SAMC21_TC1_INSTANCE_ */

109
lib/samc21/samc21/include/instance/tc2.h Normal file
View File

@@ -0,0 +1,109 @@
/**
* \file
*
* \brief Instance description for TC2
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TC2_INSTANCE_
#define _SAMC21_TC2_INSTANCE_
/* ========== Register definition for TC2 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC2_CTRLA (0x42003800) /**< \brief (TC2) Control A */
#define REG_TC2_CTRLBCLR (0x42003804) /**< \brief (TC2) Control B Clear */
#define REG_TC2_CTRLBSET (0x42003805) /**< \brief (TC2) Control B Set */
#define REG_TC2_EVCTRL (0x42003806) /**< \brief (TC2) Event Control */
#define REG_TC2_INTENCLR (0x42003808) /**< \brief (TC2) Interrupt Enable Clear */
#define REG_TC2_INTENSET (0x42003809) /**< \brief (TC2) Interrupt Enable Set */
#define REG_TC2_INTFLAG (0x4200380A) /**< \brief (TC2) Interrupt Flag Status and Clear */
#define REG_TC2_STATUS (0x4200380B) /**< \brief (TC2) Status */
#define REG_TC2_WAVE (0x4200380C) /**< \brief (TC2) Waveform Generation Control */
#define REG_TC2_DRVCTRL (0x4200380D) /**< \brief (TC2) Control C */
#define REG_TC2_DBGCTRL (0x4200380F) /**< \brief (TC2) Debug Control */
#define REG_TC2_SYNCBUSY (0x42003810) /**< \brief (TC2) Synchronization Status */
#define REG_TC2_COUNT16_COUNT (0x42003814) /**< \brief (TC2) COUNT16 Count */
#define REG_TC2_COUNT16_CC0 (0x4200381C) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
#define REG_TC2_COUNT16_CC1 (0x4200381E) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
#define REG_TC2_COUNT16_CCBUF0 (0x42003830) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC2_COUNT16_CCBUF1 (0x42003832) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC2_COUNT32_COUNT (0x42003814) /**< \brief (TC2) COUNT32 Count */
#define REG_TC2_COUNT32_CC0 (0x4200381C) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
#define REG_TC2_COUNT32_CC1 (0x42003820) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
#define REG_TC2_COUNT32_CCBUF0 (0x42003830) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC2_COUNT32_CCBUF1 (0x42003834) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC2_COUNT8_COUNT (0x42003814) /**< \brief (TC2) COUNT8 Count */
#define REG_TC2_COUNT8_PER (0x4200381B) /**< \brief (TC2) COUNT8 Period */
#define REG_TC2_COUNT8_CC0 (0x4200381C) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
#define REG_TC2_COUNT8_CC1 (0x4200381D) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
#define REG_TC2_COUNT8_PERBUF (0x4200382F) /**< \brief (TC2) COUNT8 Period Buffer */
#define REG_TC2_COUNT8_CCBUF0 (0x42003830) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC2_COUNT8_CCBUF1 (0x42003831) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
#else
#define REG_TC2_CTRLA (*(RwReg *)0x42003800UL) /**< \brief (TC2) Control A */
#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42003804UL) /**< \brief (TC2) Control B Clear */
#define REG_TC2_CTRLBSET (*(RwReg8 *)0x42003805UL) /**< \brief (TC2) Control B Set */
#define REG_TC2_EVCTRL (*(RwReg16*)0x42003806UL) /**< \brief (TC2) Event Control */
#define REG_TC2_INTENCLR (*(RwReg8 *)0x42003808UL) /**< \brief (TC2) Interrupt Enable Clear */
#define REG_TC2_INTENSET (*(RwReg8 *)0x42003809UL) /**< \brief (TC2) Interrupt Enable Set */
#define REG_TC2_INTFLAG (*(RwReg8 *)0x4200380AUL) /**< \brief (TC2) Interrupt Flag Status and Clear */
#define REG_TC2_STATUS (*(RwReg8 *)0x4200380BUL) /**< \brief (TC2) Status */
#define REG_TC2_WAVE (*(RwReg8 *)0x4200380CUL) /**< \brief (TC2) Waveform Generation Control */
#define REG_TC2_DRVCTRL (*(RwReg8 *)0x4200380DUL) /**< \brief (TC2) Control C */
#define REG_TC2_DBGCTRL (*(RwReg8 *)0x4200380FUL) /**< \brief (TC2) Debug Control */
#define REG_TC2_SYNCBUSY (*(RoReg *)0x42003810UL) /**< \brief (TC2) Synchronization Status */
#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42003814UL) /**< \brief (TC2) COUNT16 Count */
#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4200381CUL) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200381EUL) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
#define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x42003830UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x42003832UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42003814UL) /**< \brief (TC2) COUNT32 Count */
#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4200381CUL) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x42003820UL) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
#define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x42003830UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x42003834UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42003814UL) /**< \brief (TC2) COUNT8 Count */
#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4200381BUL) /**< \brief (TC2) COUNT8 Period */
#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4200381CUL) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4200381DUL) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
#define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4200382FUL) /**< \brief (TC2) COUNT8 Period Buffer */
#define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x42003830UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x42003831UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC2 peripheral ========== */
#define TC2_CC_NUM 2
#define TC2_DMAC_ID_MC_0 34
#define TC2_DMAC_ID_MC_1 35
#define TC2_DMAC_ID_MC_LSB 34
#define TC2_DMAC_ID_MC_MSB 35
#define TC2_DMAC_ID_MC_SIZE 2
#define TC2_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger
#define TC2_EXT 0
#define TC2_GCLK_ID 31
#define TC2_MASTER 1
#define TC2_OW_NUM 2
#endif /* _SAMC21_TC2_INSTANCE_ */

109
lib/samc21/samc21/include/instance/tc3.h Normal file
View File

@@ -0,0 +1,109 @@
/**
* \file
*
* \brief Instance description for TC3
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TC3_INSTANCE_
#define _SAMC21_TC3_INSTANCE_
/* ========== Register definition for TC3 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC3_CTRLA (0x42003C00) /**< \brief (TC3) Control A */
#define REG_TC3_CTRLBCLR (0x42003C04) /**< \brief (TC3) Control B Clear */
#define REG_TC3_CTRLBSET (0x42003C05) /**< \brief (TC3) Control B Set */
#define REG_TC3_EVCTRL (0x42003C06) /**< \brief (TC3) Event Control */
#define REG_TC3_INTENCLR (0x42003C08) /**< \brief (TC3) Interrupt Enable Clear */
#define REG_TC3_INTENSET (0x42003C09) /**< \brief (TC3) Interrupt Enable Set */
#define REG_TC3_INTFLAG (0x42003C0A) /**< \brief (TC3) Interrupt Flag Status and Clear */
#define REG_TC3_STATUS (0x42003C0B) /**< \brief (TC3) Status */
#define REG_TC3_WAVE (0x42003C0C) /**< \brief (TC3) Waveform Generation Control */
#define REG_TC3_DRVCTRL (0x42003C0D) /**< \brief (TC3) Control C */
#define REG_TC3_DBGCTRL (0x42003C0F) /**< \brief (TC3) Debug Control */
#define REG_TC3_SYNCBUSY (0x42003C10) /**< \brief (TC3) Synchronization Status */
#define REG_TC3_COUNT16_COUNT (0x42003C14) /**< \brief (TC3) COUNT16 Count */
#define REG_TC3_COUNT16_CC0 (0x42003C1C) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
#define REG_TC3_COUNT16_CC1 (0x42003C1E) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
#define REG_TC3_COUNT16_CCBUF0 (0x42003C30) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC3_COUNT16_CCBUF1 (0x42003C32) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC3_COUNT32_COUNT (0x42003C14) /**< \brief (TC3) COUNT32 Count */
#define REG_TC3_COUNT32_CC0 (0x42003C1C) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
#define REG_TC3_COUNT32_CC1 (0x42003C20) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
#define REG_TC3_COUNT32_CCBUF0 (0x42003C30) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC3_COUNT32_CCBUF1 (0x42003C34) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC3_COUNT8_COUNT (0x42003C14) /**< \brief (TC3) COUNT8 Count */
#define REG_TC3_COUNT8_PER (0x42003C1B) /**< \brief (TC3) COUNT8 Period */
#define REG_TC3_COUNT8_CC0 (0x42003C1C) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
#define REG_TC3_COUNT8_CC1 (0x42003C1D) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
#define REG_TC3_COUNT8_PERBUF (0x42003C2F) /**< \brief (TC3) COUNT8 Period Buffer */
#define REG_TC3_COUNT8_CCBUF0 (0x42003C30) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC3_COUNT8_CCBUF1 (0x42003C31) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
#else
#define REG_TC3_CTRLA (*(RwReg *)0x42003C00UL) /**< \brief (TC3) Control A */
#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42003C04UL) /**< \brief (TC3) Control B Clear */
#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42003C05UL) /**< \brief (TC3) Control B Set */
#define REG_TC3_EVCTRL (*(RwReg16*)0x42003C06UL) /**< \brief (TC3) Event Control */
#define REG_TC3_INTENCLR (*(RwReg8 *)0x42003C08UL) /**< \brief (TC3) Interrupt Enable Clear */
#define REG_TC3_INTENSET (*(RwReg8 *)0x42003C09UL) /**< \brief (TC3) Interrupt Enable Set */
#define REG_TC3_INTFLAG (*(RwReg8 *)0x42003C0AUL) /**< \brief (TC3) Interrupt Flag Status and Clear */
#define REG_TC3_STATUS (*(RwReg8 *)0x42003C0BUL) /**< \brief (TC3) Status */
#define REG_TC3_WAVE (*(RwReg8 *)0x42003C0CUL) /**< \brief (TC3) Waveform Generation Control */
#define REG_TC3_DRVCTRL (*(RwReg8 *)0x42003C0DUL) /**< \brief (TC3) Control C */
#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42003C0FUL) /**< \brief (TC3) Debug Control */
#define REG_TC3_SYNCBUSY (*(RoReg *)0x42003C10UL) /**< \brief (TC3) Synchronization Status */
#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42003C14UL) /**< \brief (TC3) COUNT16 Count */
#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42003C1CUL) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42003C1EUL) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x42003C30UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x42003C32UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42003C14UL) /**< \brief (TC3) COUNT32 Count */
#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42003C1CUL) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42003C20UL) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x42003C30UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x42003C34UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42003C14UL) /**< \brief (TC3) COUNT8 Count */
#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42003C1BUL) /**< \brief (TC3) COUNT8 Period */
#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42003C1CUL) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42003C1DUL) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x42003C2FUL) /**< \brief (TC3) COUNT8 Period Buffer */
#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x42003C30UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x42003C31UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC3 peripheral ========== */
#define TC3_CC_NUM 2
#define TC3_DMAC_ID_MC_0 37
#define TC3_DMAC_ID_MC_1 38
#define TC3_DMAC_ID_MC_LSB 37
#define TC3_DMAC_ID_MC_MSB 38
#define TC3_DMAC_ID_MC_SIZE 2
#define TC3_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger
#define TC3_EXT 0
#define TC3_GCLK_ID 31
#define TC3_MASTER 0
#define TC3_OW_NUM 2
#endif /* _SAMC21_TC3_INSTANCE_ */

109
lib/samc21/samc21/include/instance/tc4.h Normal file
View File

@@ -0,0 +1,109 @@
/**
* \file
*
* \brief Instance description for TC4
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TC4_INSTANCE_
#define _SAMC21_TC4_INSTANCE_
/* ========== Register definition for TC4 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC4_CTRLA (0x42004000) /**< \brief (TC4) Control A */
#define REG_TC4_CTRLBCLR (0x42004004) /**< \brief (TC4) Control B Clear */
#define REG_TC4_CTRLBSET (0x42004005) /**< \brief (TC4) Control B Set */
#define REG_TC4_EVCTRL (0x42004006) /**< \brief (TC4) Event Control */
#define REG_TC4_INTENCLR (0x42004008) /**< \brief (TC4) Interrupt Enable Clear */
#define REG_TC4_INTENSET (0x42004009) /**< \brief (TC4) Interrupt Enable Set */
#define REG_TC4_INTFLAG (0x4200400A) /**< \brief (TC4) Interrupt Flag Status and Clear */
#define REG_TC4_STATUS (0x4200400B) /**< \brief (TC4) Status */
#define REG_TC4_WAVE (0x4200400C) /**< \brief (TC4) Waveform Generation Control */
#define REG_TC4_DRVCTRL (0x4200400D) /**< \brief (TC4) Control C */
#define REG_TC4_DBGCTRL (0x4200400F) /**< \brief (TC4) Debug Control */
#define REG_TC4_SYNCBUSY (0x42004010) /**< \brief (TC4) Synchronization Status */
#define REG_TC4_COUNT16_COUNT (0x42004014) /**< \brief (TC4) COUNT16 Count */
#define REG_TC4_COUNT16_CC0 (0x4200401C) /**< \brief (TC4) COUNT16 Compare and Capture 0 */
#define REG_TC4_COUNT16_CC1 (0x4200401E) /**< \brief (TC4) COUNT16 Compare and Capture 1 */
#define REG_TC4_COUNT16_CCBUF0 (0x42004030) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC4_COUNT16_CCBUF1 (0x42004032) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC4_COUNT32_COUNT (0x42004014) /**< \brief (TC4) COUNT32 Count */
#define REG_TC4_COUNT32_CC0 (0x4200401C) /**< \brief (TC4) COUNT32 Compare and Capture 0 */
#define REG_TC4_COUNT32_CC1 (0x42004020) /**< \brief (TC4) COUNT32 Compare and Capture 1 */
#define REG_TC4_COUNT32_CCBUF0 (0x42004030) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC4_COUNT32_CCBUF1 (0x42004034) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC4_COUNT8_COUNT (0x42004014) /**< \brief (TC4) COUNT8 Count */
#define REG_TC4_COUNT8_PER (0x4200401B) /**< \brief (TC4) COUNT8 Period */
#define REG_TC4_COUNT8_CC0 (0x4200401C) /**< \brief (TC4) COUNT8 Compare and Capture 0 */
#define REG_TC4_COUNT8_CC1 (0x4200401D) /**< \brief (TC4) COUNT8 Compare and Capture 1 */
#define REG_TC4_COUNT8_PERBUF (0x4200402F) /**< \brief (TC4) COUNT8 Period Buffer */
#define REG_TC4_COUNT8_CCBUF0 (0x42004030) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC4_COUNT8_CCBUF1 (0x42004031) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */
#else
#define REG_TC4_CTRLA (*(RwReg *)0x42004000UL) /**< \brief (TC4) Control A */
#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42004004UL) /**< \brief (TC4) Control B Clear */
#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42004005UL) /**< \brief (TC4) Control B Set */
#define REG_TC4_EVCTRL (*(RwReg16*)0x42004006UL) /**< \brief (TC4) Event Control */
#define REG_TC4_INTENCLR (*(RwReg8 *)0x42004008UL) /**< \brief (TC4) Interrupt Enable Clear */
#define REG_TC4_INTENSET (*(RwReg8 *)0x42004009UL) /**< \brief (TC4) Interrupt Enable Set */
#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200400AUL) /**< \brief (TC4) Interrupt Flag Status and Clear */
#define REG_TC4_STATUS (*(RwReg8 *)0x4200400BUL) /**< \brief (TC4) Status */
#define REG_TC4_WAVE (*(RwReg8 *)0x4200400CUL) /**< \brief (TC4) Waveform Generation Control */
#define REG_TC4_DRVCTRL (*(RwReg8 *)0x4200400DUL) /**< \brief (TC4) Control C */
#define REG_TC4_DBGCTRL (*(RwReg8 *)0x4200400FUL) /**< \brief (TC4) Debug Control */
#define REG_TC4_SYNCBUSY (*(RoReg *)0x42004010UL) /**< \brief (TC4) Synchronization Status */
#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42004014UL) /**< \brief (TC4) COUNT16 Count */
#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x4200401CUL) /**< \brief (TC4) COUNT16 Compare and Capture 0 */
#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200401EUL) /**< \brief (TC4) COUNT16 Compare and Capture 1 */
#define REG_TC4_COUNT16_CCBUF0 (*(RwReg16*)0x42004030UL) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC4_COUNT16_CCBUF1 (*(RwReg16*)0x42004032UL) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42004014UL) /**< \brief (TC4) COUNT32 Count */
#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x4200401CUL) /**< \brief (TC4) COUNT32 Compare and Capture 0 */
#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x42004020UL) /**< \brief (TC4) COUNT32 Compare and Capture 1 */
#define REG_TC4_COUNT32_CCBUF0 (*(RwReg *)0x42004030UL) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC4_COUNT32_CCBUF1 (*(RwReg *)0x42004034UL) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42004014UL) /**< \brief (TC4) COUNT8 Count */
#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x4200401BUL) /**< \brief (TC4) COUNT8 Period */
#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x4200401CUL) /**< \brief (TC4) COUNT8 Compare and Capture 0 */
#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x4200401DUL) /**< \brief (TC4) COUNT8 Compare and Capture 1 */
#define REG_TC4_COUNT8_PERBUF (*(RwReg8 *)0x4200402FUL) /**< \brief (TC4) COUNT8 Period Buffer */
#define REG_TC4_COUNT8_CCBUF0 (*(RwReg8 *)0x42004030UL) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC4_COUNT8_CCBUF1 (*(RwReg8 *)0x42004031UL) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC4 peripheral ========== */
#define TC4_CC_NUM 2
#define TC4_DMAC_ID_MC_0 40
#define TC4_DMAC_ID_MC_1 41
#define TC4_DMAC_ID_MC_LSB 40
#define TC4_DMAC_ID_MC_MSB 41
#define TC4_DMAC_ID_MC_SIZE 2
#define TC4_DMAC_ID_OVF 39 // Indexes of DMA Overflow trigger
#define TC4_EXT 0
#define TC4_GCLK_ID 32
#define TC4_MASTER 0
#define TC4_OW_NUM 2
#endif /* _SAMC21_TC4_INSTANCE_ */

115
lib/samc21/samc21/include/instance/tcc0.h Normal file
View File

@@ -0,0 +1,115 @@
/**
* \file
*
* \brief Instance description for TCC0
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TCC0_INSTANCE_
#define _SAMC21_TCC0_INSTANCE_
/* ========== Register definition for TCC0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TCC0_CTRLA (0x42002400) /**< \brief (TCC0) Control A */
#define REG_TCC0_CTRLBCLR (0x42002404) /**< \brief (TCC0) Control B Clear */
#define REG_TCC0_CTRLBSET (0x42002405) /**< \brief (TCC0) Control B Set */
#define REG_TCC0_SYNCBUSY (0x42002408) /**< \brief (TCC0) Synchronization Busy */
#define REG_TCC0_FCTRLA (0x4200240C) /**< \brief (TCC0) Recoverable Fault A Configuration */
#define REG_TCC0_FCTRLB (0x42002410) /**< \brief (TCC0) Recoverable Fault B Configuration */
#define REG_TCC0_WEXCTRL (0x42002414) /**< \brief (TCC0) Waveform Extension Configuration */
#define REG_TCC0_DRVCTRL (0x42002418) /**< \brief (TCC0) Driver Control */
#define REG_TCC0_DBGCTRL (0x4200241E) /**< \brief (TCC0) Debug Control */
#define REG_TCC0_EVCTRL (0x42002420) /**< \brief (TCC0) Event Control */
#define REG_TCC0_INTENCLR (0x42002424) /**< \brief (TCC0) Interrupt Enable Clear */
#define REG_TCC0_INTENSET (0x42002428) /**< \brief (TCC0) Interrupt Enable Set */
#define REG_TCC0_INTFLAG (0x4200242C) /**< \brief (TCC0) Interrupt Flag Status and Clear */
#define REG_TCC0_STATUS (0x42002430) /**< \brief (TCC0) Status */
#define REG_TCC0_COUNT (0x42002434) /**< \brief (TCC0) Count */
#define REG_TCC0_PATT (0x42002438) /**< \brief (TCC0) Pattern */
#define REG_TCC0_WAVE (0x4200243C) /**< \brief (TCC0) Waveform Control */
#define REG_TCC0_PER (0x42002440) /**< \brief (TCC0) Period */
#define REG_TCC0_CC0 (0x42002444) /**< \brief (TCC0) Compare and Capture 0 */
#define REG_TCC0_CC1 (0x42002448) /**< \brief (TCC0) Compare and Capture 1 */
#define REG_TCC0_CC2 (0x4200244C) /**< \brief (TCC0) Compare and Capture 2 */
#define REG_TCC0_CC3 (0x42002450) /**< \brief (TCC0) Compare and Capture 3 */
#define REG_TCC0_PATTBUF (0x42002464) /**< \brief (TCC0) Pattern Buffer */
#define REG_TCC0_PERBUF (0x4200246C) /**< \brief (TCC0) Period Buffer */
#define REG_TCC0_CCBUF0 (0x42002470) /**< \brief (TCC0) Compare and Capture Buffer 0 */
#define REG_TCC0_CCBUF1 (0x42002474) /**< \brief (TCC0) Compare and Capture Buffer 1 */
#define REG_TCC0_CCBUF2 (0x42002478) /**< \brief (TCC0) Compare and Capture Buffer 2 */
#define REG_TCC0_CCBUF3 (0x4200247C) /**< \brief (TCC0) Compare and Capture Buffer 3 */
#else
#define REG_TCC0_CTRLA (*(RwReg *)0x42002400UL) /**< \brief (TCC0) Control A */
#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002404UL) /**< \brief (TCC0) Control B Clear */
#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002405UL) /**< \brief (TCC0) Control B Set */
#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002408UL) /**< \brief (TCC0) Synchronization Busy */
#define REG_TCC0_FCTRLA (*(RwReg *)0x4200240CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */
#define REG_TCC0_FCTRLB (*(RwReg *)0x42002410UL) /**< \brief (TCC0) Recoverable Fault B Configuration */
#define REG_TCC0_WEXCTRL (*(RwReg *)0x42002414UL) /**< \brief (TCC0) Waveform Extension Configuration */
#define REG_TCC0_DRVCTRL (*(RwReg *)0x42002418UL) /**< \brief (TCC0) Driver Control */
#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200241EUL) /**< \brief (TCC0) Debug Control */
#define REG_TCC0_EVCTRL (*(RwReg *)0x42002420UL) /**< \brief (TCC0) Event Control */
#define REG_TCC0_INTENCLR (*(RwReg *)0x42002424UL) /**< \brief (TCC0) Interrupt Enable Clear */
#define REG_TCC0_INTENSET (*(RwReg *)0x42002428UL) /**< \brief (TCC0) Interrupt Enable Set */
#define REG_TCC0_INTFLAG (*(RwReg *)0x4200242CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */
#define REG_TCC0_STATUS (*(RwReg *)0x42002430UL) /**< \brief (TCC0) Status */
#define REG_TCC0_COUNT (*(RwReg *)0x42002434UL) /**< \brief (TCC0) Count */
#define REG_TCC0_PATT (*(RwReg16*)0x42002438UL) /**< \brief (TCC0) Pattern */
#define REG_TCC0_WAVE (*(RwReg *)0x4200243CUL) /**< \brief (TCC0) Waveform Control */
#define REG_TCC0_PER (*(RwReg *)0x42002440UL) /**< \brief (TCC0) Period */
#define REG_TCC0_CC0 (*(RwReg *)0x42002444UL) /**< \brief (TCC0) Compare and Capture 0 */
#define REG_TCC0_CC1 (*(RwReg *)0x42002448UL) /**< \brief (TCC0) Compare and Capture 1 */
#define REG_TCC0_CC2 (*(RwReg *)0x4200244CUL) /**< \brief (TCC0) Compare and Capture 2 */
#define REG_TCC0_CC3 (*(RwReg *)0x42002450UL) /**< \brief (TCC0) Compare and Capture 3 */
#define REG_TCC0_PATTBUF (*(RwReg16*)0x42002464UL) /**< \brief (TCC0) Pattern Buffer */
#define REG_TCC0_PERBUF (*(RwReg *)0x4200246CUL) /**< \brief (TCC0) Period Buffer */
#define REG_TCC0_CCBUF0 (*(RwReg *)0x42002470UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */
#define REG_TCC0_CCBUF1 (*(RwReg *)0x42002474UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */
#define REG_TCC0_CCBUF2 (*(RwReg *)0x42002478UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */
#define REG_TCC0_CCBUF3 (*(RwReg *)0x4200247CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TCC0 peripheral ========== */
#define TCC0_CC_NUM 4 // Number of Compare/Capture units
#define TCC0_DITHERING 1 // Dithering feature implemented
#define TCC0_DMAC_ID_MC_0 17
#define TCC0_DMAC_ID_MC_1 18
#define TCC0_DMAC_ID_MC_2 19
#define TCC0_DMAC_ID_MC_3 20
#define TCC0_DMAC_ID_MC_LSB 17
#define TCC0_DMAC_ID_MC_MSB 20
#define TCC0_DMAC_ID_MC_SIZE 4
#define TCC0_DMAC_ID_OVF 16 // DMA overflow/underflow/retrigger trigger
#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
#define TCC0_EXT 31 // Coding of implemented extended features
#define TCC0_GCLK_ID 28 // Index of Generic Clock
#define TCC0_OTMX 1 // Output Matrix feature implemented
#define TCC0_OW_NUM 8 // Number of Output Waveforms
#define TCC0_PG 1 // Pattern Generation feature implemented
#define TCC0_SIZE 24
#define TCC0_SWAP 1 // DTI outputs swap feature implemented
#define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave
#endif /* _SAMC21_TCC0_INSTANCE_ */

103
lib/samc21/samc21/include/instance/tcc1.h Normal file
View File

@@ -0,0 +1,103 @@
/**
* \file
*
* \brief Instance description for TCC1
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TCC1_INSTANCE_
#define _SAMC21_TCC1_INSTANCE_
/* ========== Register definition for TCC1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TCC1_CTRLA (0x42002800) /**< \brief (TCC1) Control A */
#define REG_TCC1_CTRLBCLR (0x42002804) /**< \brief (TCC1) Control B Clear */
#define REG_TCC1_CTRLBSET (0x42002805) /**< \brief (TCC1) Control B Set */
#define REG_TCC1_SYNCBUSY (0x42002808) /**< \brief (TCC1) Synchronization Busy */
#define REG_TCC1_FCTRLA (0x4200280C) /**< \brief (TCC1) Recoverable Fault A Configuration */
#define REG_TCC1_FCTRLB (0x42002810) /**< \brief (TCC1) Recoverable Fault B Configuration */
#define REG_TCC1_DRVCTRL (0x42002818) /**< \brief (TCC1) Driver Control */
#define REG_TCC1_DBGCTRL (0x4200281E) /**< \brief (TCC1) Debug Control */
#define REG_TCC1_EVCTRL (0x42002820) /**< \brief (TCC1) Event Control */
#define REG_TCC1_INTENCLR (0x42002824) /**< \brief (TCC1) Interrupt Enable Clear */
#define REG_TCC1_INTENSET (0x42002828) /**< \brief (TCC1) Interrupt Enable Set */
#define REG_TCC1_INTFLAG (0x4200282C) /**< \brief (TCC1) Interrupt Flag Status and Clear */
#define REG_TCC1_STATUS (0x42002830) /**< \brief (TCC1) Status */
#define REG_TCC1_COUNT (0x42002834) /**< \brief (TCC1) Count */
#define REG_TCC1_PATT (0x42002838) /**< \brief (TCC1) Pattern */
#define REG_TCC1_WAVE (0x4200283C) /**< \brief (TCC1) Waveform Control */
#define REG_TCC1_PER (0x42002840) /**< \brief (TCC1) Period */
#define REG_TCC1_CC0 (0x42002844) /**< \brief (TCC1) Compare and Capture 0 */
#define REG_TCC1_CC1 (0x42002848) /**< \brief (TCC1) Compare and Capture 1 */
#define REG_TCC1_PATTBUF (0x42002864) /**< \brief (TCC1) Pattern Buffer */
#define REG_TCC1_PERBUF (0x4200286C) /**< \brief (TCC1) Period Buffer */
#define REG_TCC1_CCBUF0 (0x42002870) /**< \brief (TCC1) Compare and Capture Buffer 0 */
#define REG_TCC1_CCBUF1 (0x42002874) /**< \brief (TCC1) Compare and Capture Buffer 1 */
#else
#define REG_TCC1_CTRLA (*(RwReg *)0x42002800UL) /**< \brief (TCC1) Control A */
#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002804UL) /**< \brief (TCC1) Control B Clear */
#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002805UL) /**< \brief (TCC1) Control B Set */
#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002808UL) /**< \brief (TCC1) Synchronization Busy */
#define REG_TCC1_FCTRLA (*(RwReg *)0x4200280CUL) /**< \brief (TCC1) Recoverable Fault A Configuration */
#define REG_TCC1_FCTRLB (*(RwReg *)0x42002810UL) /**< \brief (TCC1) Recoverable Fault B Configuration */
#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002818UL) /**< \brief (TCC1) Driver Control */
#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200281EUL) /**< \brief (TCC1) Debug Control */
#define REG_TCC1_EVCTRL (*(RwReg *)0x42002820UL) /**< \brief (TCC1) Event Control */
#define REG_TCC1_INTENCLR (*(RwReg *)0x42002824UL) /**< \brief (TCC1) Interrupt Enable Clear */
#define REG_TCC1_INTENSET (*(RwReg *)0x42002828UL) /**< \brief (TCC1) Interrupt Enable Set */
#define REG_TCC1_INTFLAG (*(RwReg *)0x4200282CUL) /**< \brief (TCC1) Interrupt Flag Status and Clear */
#define REG_TCC1_STATUS (*(RwReg *)0x42002830UL) /**< \brief (TCC1) Status */
#define REG_TCC1_COUNT (*(RwReg *)0x42002834UL) /**< \brief (TCC1) Count */
#define REG_TCC1_PATT (*(RwReg16*)0x42002838UL) /**< \brief (TCC1) Pattern */
#define REG_TCC1_WAVE (*(RwReg *)0x4200283CUL) /**< \brief (TCC1) Waveform Control */
#define REG_TCC1_PER (*(RwReg *)0x42002840UL) /**< \brief (TCC1) Period */
#define REG_TCC1_CC0 (*(RwReg *)0x42002844UL) /**< \brief (TCC1) Compare and Capture 0 */
#define REG_TCC1_CC1 (*(RwReg *)0x42002848UL) /**< \brief (TCC1) Compare and Capture 1 */
#define REG_TCC1_PATTBUF (*(RwReg16*)0x42002864UL) /**< \brief (TCC1) Pattern Buffer */
#define REG_TCC1_PERBUF (*(RwReg *)0x4200286CUL) /**< \brief (TCC1) Period Buffer */
#define REG_TCC1_CCBUF0 (*(RwReg *)0x42002870UL) /**< \brief (TCC1) Compare and Capture Buffer 0 */
#define REG_TCC1_CCBUF1 (*(RwReg *)0x42002874UL) /**< \brief (TCC1) Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TCC1 peripheral ========== */
#define TCC1_CC_NUM 2 // Number of Compare/Capture units
#define TCC1_DITHERING 1 // Dithering feature implemented
#define TCC1_DMAC_ID_MC_0 22
#define TCC1_DMAC_ID_MC_1 23
#define TCC1_DMAC_ID_MC_LSB 22
#define TCC1_DMAC_ID_MC_MSB 23
#define TCC1_DMAC_ID_MC_SIZE 2
#define TCC1_DMAC_ID_OVF 21 // DMA overflow/underflow/retrigger trigger
#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented
#define TCC1_EXT 24 // Coding of implemented extended features
#define TCC1_GCLK_ID 28 // Index of Generic Clock
#define TCC1_OTMX 0 // Output Matrix feature implemented
#define TCC1_OW_NUM 4 // Number of Output Waveforms
#define TCC1_PG 1 // Pattern Generation feature implemented
#define TCC1_SIZE 24
#define TCC1_SWAP 0 // DTI outputs swap feature implemented
#define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave
#endif /* _SAMC21_TCC1_INSTANCE_ */

99
lib/samc21/samc21/include/instance/tcc2.h Normal file
View File

@@ -0,0 +1,99 @@
/**
* \file
*
* \brief Instance description for TCC2
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TCC2_INSTANCE_
#define _SAMC21_TCC2_INSTANCE_
/* ========== Register definition for TCC2 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TCC2_CTRLA (0x42002C00) /**< \brief (TCC2) Control A */
#define REG_TCC2_CTRLBCLR (0x42002C04) /**< \brief (TCC2) Control B Clear */
#define REG_TCC2_CTRLBSET (0x42002C05) /**< \brief (TCC2) Control B Set */
#define REG_TCC2_SYNCBUSY (0x42002C08) /**< \brief (TCC2) Synchronization Busy */
#define REG_TCC2_FCTRLA (0x42002C0C) /**< \brief (TCC2) Recoverable Fault A Configuration */
#define REG_TCC2_FCTRLB (0x42002C10) /**< \brief (TCC2) Recoverable Fault B Configuration */
#define REG_TCC2_DRVCTRL (0x42002C18) /**< \brief (TCC2) Driver Control */
#define REG_TCC2_DBGCTRL (0x42002C1E) /**< \brief (TCC2) Debug Control */
#define REG_TCC2_EVCTRL (0x42002C20) /**< \brief (TCC2) Event Control */
#define REG_TCC2_INTENCLR (0x42002C24) /**< \brief (TCC2) Interrupt Enable Clear */
#define REG_TCC2_INTENSET (0x42002C28) /**< \brief (TCC2) Interrupt Enable Set */
#define REG_TCC2_INTFLAG (0x42002C2C) /**< \brief (TCC2) Interrupt Flag Status and Clear */
#define REG_TCC2_STATUS (0x42002C30) /**< \brief (TCC2) Status */
#define REG_TCC2_COUNT (0x42002C34) /**< \brief (TCC2) Count */
#define REG_TCC2_WAVE (0x42002C3C) /**< \brief (TCC2) Waveform Control */
#define REG_TCC2_PER (0x42002C40) /**< \brief (TCC2) Period */
#define REG_TCC2_CC0 (0x42002C44) /**< \brief (TCC2) Compare and Capture 0 */
#define REG_TCC2_CC1 (0x42002C48) /**< \brief (TCC2) Compare and Capture 1 */
#define REG_TCC2_PERBUF (0x42002C6C) /**< \brief (TCC2) Period Buffer */
#define REG_TCC2_CCBUF0 (0x42002C70) /**< \brief (TCC2) Compare and Capture Buffer 0 */
#define REG_TCC2_CCBUF1 (0x42002C74) /**< \brief (TCC2) Compare and Capture Buffer 1 */
#else
#define REG_TCC2_CTRLA (*(RwReg *)0x42002C00UL) /**< \brief (TCC2) Control A */
#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002C04UL) /**< \brief (TCC2) Control B Clear */
#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002C05UL) /**< \brief (TCC2) Control B Set */
#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002C08UL) /**< \brief (TCC2) Synchronization Busy */
#define REG_TCC2_FCTRLA (*(RwReg *)0x42002C0CUL) /**< \brief (TCC2) Recoverable Fault A Configuration */
#define REG_TCC2_FCTRLB (*(RwReg *)0x42002C10UL) /**< \brief (TCC2) Recoverable Fault B Configuration */
#define REG_TCC2_DRVCTRL (*(RwReg *)0x42002C18UL) /**< \brief (TCC2) Driver Control */
#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x42002C1EUL) /**< \brief (TCC2) Debug Control */
#define REG_TCC2_EVCTRL (*(RwReg *)0x42002C20UL) /**< \brief (TCC2) Event Control */
#define REG_TCC2_INTENCLR (*(RwReg *)0x42002C24UL) /**< \brief (TCC2) Interrupt Enable Clear */
#define REG_TCC2_INTENSET (*(RwReg *)0x42002C28UL) /**< \brief (TCC2) Interrupt Enable Set */
#define REG_TCC2_INTFLAG (*(RwReg *)0x42002C2CUL) /**< \brief (TCC2) Interrupt Flag Status and Clear */
#define REG_TCC2_STATUS (*(RwReg *)0x42002C30UL) /**< \brief (TCC2) Status */
#define REG_TCC2_COUNT (*(RwReg *)0x42002C34UL) /**< \brief (TCC2) Count */
#define REG_TCC2_WAVE (*(RwReg *)0x42002C3CUL) /**< \brief (TCC2) Waveform Control */
#define REG_TCC2_PER (*(RwReg *)0x42002C40UL) /**< \brief (TCC2) Period */
#define REG_TCC2_CC0 (*(RwReg *)0x42002C44UL) /**< \brief (TCC2) Compare and Capture 0 */
#define REG_TCC2_CC1 (*(RwReg *)0x42002C48UL) /**< \brief (TCC2) Compare and Capture 1 */
#define REG_TCC2_PERBUF (*(RwReg *)0x42002C6CUL) /**< \brief (TCC2) Period Buffer */
#define REG_TCC2_CCBUF0 (*(RwReg *)0x42002C70UL) /**< \brief (TCC2) Compare and Capture Buffer 0 */
#define REG_TCC2_CCBUF1 (*(RwReg *)0x42002C74UL) /**< \brief (TCC2) Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TCC2 peripheral ========== */
#define TCC2_CC_NUM 2 // Number of Compare/Capture units
#define TCC2_DITHERING 0 // Dithering feature implemented
#define TCC2_DMAC_ID_MC_0 25
#define TCC2_DMAC_ID_MC_1 26
#define TCC2_DMAC_ID_MC_LSB 25
#define TCC2_DMAC_ID_MC_MSB 26
#define TCC2_DMAC_ID_MC_SIZE 2
#define TCC2_DMAC_ID_OVF 24 // DMA overflow/underflow/retrigger trigger
#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
#define TCC2_EXT 0 // Coding of implemented extended features
#define TCC2_GCLK_ID 29 // Index of Generic Clock
#define TCC2_OTMX 0 // Output Matrix feature implemented
#define TCC2_OW_NUM 2 // Number of Output Waveforms
#define TCC2_PG 0 // Pattern Generation feature implemented
#define TCC2_SIZE 16
#define TCC2_SWAP 0 // DTI outputs swap feature implemented
#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
#endif /* _SAMC21_TCC2_INSTANCE_ */

74
lib/samc21/samc21/include/instance/tsens.h Normal file
View File

@@ -0,0 +1,74 @@
/**
* \file
*
* \brief Instance description for TSENS
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TSENS_INSTANCE_
#define _SAMC21_TSENS_INSTANCE_
/* ========== Register definition for TSENS peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TSENS_CTRLA (0x40003000) /**< \brief (TSENS) Control A Register */
#define REG_TSENS_CTRLB (0x40003001) /**< \brief (TSENS) Control B Register */
#define REG_TSENS_CTRLC (0x40003002) /**< \brief (TSENS) Control C Register */
#define REG_TSENS_EVCTRL (0x40003003) /**< \brief (TSENS) Event Control Register */
#define REG_TSENS_INTENCLR (0x40003004) /**< \brief (TSENS) Interrupt Enable Clear Register */
#define REG_TSENS_INTENSET (0x40003005) /**< \brief (TSENS) Interrupt Enable Set Register */
#define REG_TSENS_INTFLAG (0x40003006) /**< \brief (TSENS) Interrupt Flag Status and Clear Register */
#define REG_TSENS_STATUS (0x40003007) /**< \brief (TSENS) Status Register */
#define REG_TSENS_SYNCBUSY (0x40003008) /**< \brief (TSENS) Synchronization Busy Register */
#define REG_TSENS_VALUE (0x4000300C) /**< \brief (TSENS) Value Register */
#define REG_TSENS_WINLT (0x40003010) /**< \brief (TSENS) Window Monitor Lower Threshold Register */
#define REG_TSENS_WINUT (0x40003014) /**< \brief (TSENS) Window Monitor Upper Threshold Register */
#define REG_TSENS_GAIN (0x40003018) /**< \brief (TSENS) Gain Register */
#define REG_TSENS_OFFSET (0x4000301C) /**< \brief (TSENS) Offset Register */
#define REG_TSENS_CAL (0x40003020) /**< \brief (TSENS) Calibration Register */
#define REG_TSENS_DBGCTRL (0x40003024) /**< \brief (TSENS) Debug Control Register */
#else
#define REG_TSENS_CTRLA (*(RwReg8 *)0x40003000UL) /**< \brief (TSENS) Control A Register */
#define REG_TSENS_CTRLB (*(WoReg8 *)0x40003001UL) /**< \brief (TSENS) Control B Register */
#define REG_TSENS_CTRLC (*(RwReg8 *)0x40003002UL) /**< \brief (TSENS) Control C Register */
#define REG_TSENS_EVCTRL (*(RwReg8 *)0x40003003UL) /**< \brief (TSENS) Event Control Register */
#define REG_TSENS_INTENCLR (*(RwReg8 *)0x40003004UL) /**< \brief (TSENS) Interrupt Enable Clear Register */
#define REG_TSENS_INTENSET (*(RwReg8 *)0x40003005UL) /**< \brief (TSENS) Interrupt Enable Set Register */
#define REG_TSENS_INTFLAG (*(RwReg8 *)0x40003006UL) /**< \brief (TSENS) Interrupt Flag Status and Clear Register */
#define REG_TSENS_STATUS (*(RoReg8 *)0x40003007UL) /**< \brief (TSENS) Status Register */
#define REG_TSENS_SYNCBUSY (*(RoReg *)0x40003008UL) /**< \brief (TSENS) Synchronization Busy Register */
#define REG_TSENS_VALUE (*(RoReg *)0x4000300CUL) /**< \brief (TSENS) Value Register */
#define REG_TSENS_WINLT (*(RwReg *)0x40003010UL) /**< \brief (TSENS) Window Monitor Lower Threshold Register */
#define REG_TSENS_WINUT (*(RwReg *)0x40003014UL) /**< \brief (TSENS) Window Monitor Upper Threshold Register */
#define REG_TSENS_GAIN (*(RwReg *)0x40003018UL) /**< \brief (TSENS) Gain Register */
#define REG_TSENS_OFFSET (*(RwReg *)0x4000301CUL) /**< \brief (TSENS) Offset Register */
#define REG_TSENS_CAL (*(RwReg *)0x40003020UL) /**< \brief (TSENS) Calibration Register */
#define REG_TSENS_DBGCTRL (*(RwReg8 *)0x40003024UL) /**< \brief (TSENS) Debug Control Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TSENS peripheral ========== */
#define TSENS_DMAC_ID_RESRDY 1 // Index of DMA RESRDY trigger
#define TSENS_GCLK_ID 5 // Index of Generic Clock
#endif /* _SAMC21_TSENS_INSTANCE_ */

55
lib/samc21/samc21/include/instance/wdt.h Normal file
View File

@@ -0,0 +1,55 @@
/**
* \file
*
* \brief Instance description for WDT
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_WDT_INSTANCE_
#define _SAMC21_WDT_INSTANCE_
/* ========== Register definition for WDT peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */
#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */
#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */
#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */
#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */
#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */
#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */
#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */
#else
#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */
#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */
#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */
#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */
#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */
#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */
#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */
#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMC21_WDT_INSTANCE_ */